System Bus Routing Guidelines; Design Recommendations; System Bus Signals; System Bus Signal Groups - Intel Pentium M Processor Design Manual

System Bus Routing Guidelines

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5.1 Intel

Design Recommendations

For proper operation of the Intel
necessary that the system designer meet the timing and voltage specification of each component.
These following recommendations are Intel's recommended guidelines based on extensive
simulation and experimentation that make assumptions, which may be different than a customer's
system design. The most accurate way to understand the signal integrity and timing of the Intel
Pentium M processor system bus in your platform is by performing a comprehensive simulation
analysis. It is possible that adjustments to trace impedance, line length, termination impedance,
board stack-up, and other parameters may be made to improve system performance.
The following sections discuss the design recommendations for the processor's data, address, and
strobe signals.
5.1.1

System Bus Signals

Table 14
refer to the Intel
process with 2-MB L2 cache Datasheet, and the Intel
(MCH) Datasheet.
Table 14.

System Bus Signal Groups

Signal Group
AGTL+ Common Clock Input
AGTL+ Common Clock I/O
AGTL+ Source Synchronous
I/O: 4X Group
AGTL+ Source Synchronous
I/O: 2X Group
AGTL+ Strobes
Asynchronous GTL+ Input
Asynchronous GTL+ Output
System Bus Clock
TAP Input
TAP Output
Power/Other
Design Guide
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Intel Pentium
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Pentium M Processor System Bus
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Pentium
lists the system bus signals and their corresponding types. For more signal information
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Pentium® M Processor Datasheet , Intel
Synchronous to BCLK
Synchronous to BCLK
Synchronous to assoc.
strobe
Synchronous to assoc.
strobe
Synchronous to BCLK [1:0] ADSTB[1:0]#, DSTBN[3:0]#, DSTBP[3:0]#
Asynchronous
Asynchronous
Clock
Synchronous to TCK
Synchronous to TCK
Power/Other
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M Processor and Intel
System Bus Routing Guidelines
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M processor and the Intel
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Pentium® M Processor on the 90 nm
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E7501 Chipset Memory Controller Hub
Type
BPRI#, DEFER#, RESET#, PREQ#, RS[2:0]#,
TRDY#
ADS#, BNR#,BPM[3:0]#, BR0#, DBSY#,
DRDY#, HIT#, HITM#, LOCK#, PRDY#
D[63:0]#, DINV[3:0]#
A[31:3]#, REQ[4:0]#
A20M#, IGNNE#, INIT#, LINT1/NMI, LINT0/
INTR, SMI#, STPCLK#, SLP#
DBR#, FERR#, IERR#, PROCHOT#, PSI#,
THERMTRIP#
BCLK[1:0]
ITP_CLK[1:0], TCK, TDI, TMS, TRST#
TDO
GTLREF, COMP[3:0], PWRGOOD, RSVD,
TEST[3:1], THERMDA, THERMDC, VCC,
VCCA[3:1], VCCP, VCCQ[1:0], VID[5:0], VSS,
VCCSENSE, VSSSENSE
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E7501 Chipset Platform
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E7501 chipset, it is
Signals
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