Processor Host Bus Design; Initial Timing Analysis; System Timing Equations; System Timing Terms - Intel Pentium III Processor 512K Design Manual

3.0

Processor Host Bus Design

3.1

Initial Timing Analysis

To determine the available flight time window, perform an initial timing analysis. Analysis of setup
and hold conditions will determine the minimum and maximum flight time bounds for the system
bus. Use the following equations to establish the system flight time limits.
Table 3.

System Timing Equations

T >= T
flight,min
T
flight,max
Table 4. System Timing Terms
Term
T
cycle
T
flight,min
T
flight,max
T
co,max
T
co,min
T
su
T
hold
T
skew
T
jit
T
adj
Component timings for the LV Intel Pentium
®
Intel Pentium
vendor for documentation concerning the chipset component timing.
Table 5 provides recommended values for system timings. Skew and jitter values for the clock
generator device come from the clock driver vendor's datasheet. The PCB skew specification is
based on the results of extensive simulations performed by Intel engineers. The T
on Intel's experience with systems that use previous generations of processors.
Design Guide
®
LV Intel
- T + T
hold co,min skew
<= T - T - T - T
cycle co,max su skew
System cycle time. Defined as the reciprocal of the frequency.
Minimum system flight time.
Maximum system flight time.
Maximum driver delay from input clock to output data.
Minimum driver delay from input clock to output data.
Minimum setup time. Defined as the time for which the input data must be valid prior to the
input clock.
Minimum hold time. Defined as the time for which the input data must remain valid after the
input clock.
Clock generator skew. Defined as the maximum delay variation between output clock
signals from the system clock generator, the maximum delay variation between clock
signals due to system board variation and chipset loading variation.
Clock jitter. Defined as the maximum edge to edge variation in a given clock signal.
Multi-bit timing adjustment factor. This term accounts for the additional delay that occurs in
the network when multiple data bits switch in the same cycle. The adjustment factor
includes mechanisms such as package and PCB crosstalk, high inductance current return
paths, and simultaneous switching noise.
®
III Processor 512K Datasheet (order number 273673). Please contact your chipset
®
Pentium III Processor 512K Dual Processor Platform
Equation
- T - T
jit adj
Description
processor 512K are available in the Low Voltage
III
value is based
adj
13