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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz
3.14.
GTL+ Bus Specifications
The GTL+ bus must be routed in a daisy-chain
fashion with termination resistors at each end of
every signal trace. These termination resistors are
placed between the ends of the signal trace and the
V
voltage supply and generally are chosen to
TT
approximate the board impedance. The valid high
and low levels are determined by the input buffers
Symbol
Parameter
V
Bus Termination
TT
Voltage
V
Input Reference
REF
Voltage
NOTES:
•
V
should be created from V
REF
3.15.
AC Specifications
Table 9 through Table 16 list the AC specifications
associated with the Pentium Pro processor. Timing
Diagrams
begin
with
specifications are broken into categories. Table 9
contains the clock specifications, Table 11 and
Table 12 contain the GTL+ specifications, Table 13 is
the 3.3 V tolerant Signal group specifications,
Table 14 contains timings for the reset conditions,
24
Table 8. GTL+ Bus Voltage Specifications
Min
1.35
2/3 V
-2%
TT
by a voltage divider of 1% resistors.
TT
Figure 13.
The
AC
using a reference voltage called V
the nominal specifications for the GTL+ termination
voltage (V
) and the GTL+ reference voltage (V
TT
It is important that the printed circuit board
impedance be specified and held to a ±20%
tolerance, and that the intrinsic trace capacitance for
the GTL+ signal group traces is known. For more
details on GTL+, see Section 4.
Typical
Max
1.5
1.65
2/3 V
2/3 V
+2%
TT
TT
Table 15 covers APIC bus timing, and Table 16
covers Boundary Scan timing.
All AC specifications for the GTL+ signal group are
relative to the rising edge of the BCLK input. All
GTL+ timings are referenced to V
'1' logic levels unless otherwise specified.
Care should be taken to read all notes associated
with a particular timing parameter.
E
. Table 8 lists
REF
).
REF
Units
Notes
V
±10%
V
±2%, 1
for both '0' and
REF
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