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10.1.4.
Mobile IDE Swap Bay Support
Systems that require the support for an IDE "hot" swap drive bay can be designed to utilize the ICH4-
M's IDE interface disable feature to achieve this functionality. To support a mobile "hot" swap bay, the
ICH4-M allows the IDE output signals to be tri-stated or driven low and input buffers to be turned off.
This requires certain hardware and software requirements to be met for proper operation.
From a hardware perspective, the equivalent of two spare control signals (e.g. GPIO's) and a FET are
needed to properly utilize the IDE tri-state feature. An IDE drive must have a reset signal (i.e. first
additional control signal) driving its reset pin and a power supply that is isolated from the rest of the
IDE interface. To isolate the power supplied to the IDE drive bay, a second additional control signal is
needed to control the enabling/disabling of a FET that supplies a separate plane flood powering the IDE
drive and its interface.
Although actual hardware implementations may vary, the isolated reset signal and power plane
are strict requirements. Systems that connect the IDE swap bay drive to the same power plane and
reset signals of the ICH4-M should not use this IDE tri-state feature. Many IDE drives use the control
and address lines as straps that are used to enter test modes. If the IDE drive is powered up along with
the ICH4-M while the IDE interface is tri-stated rather than being driven to the default state, then the
IDE drive could potentially enter a test mode. To avoid such a situation, the aforementioned hardware
requirements or equivalent solution should be implemented.
10.1.4.1. ICH4-M IDE Interface Tri-State Feature
The new IDE interface tri-state capabilities of the ICH4-M also include a number of configuration bits
that must be programmed accordingly for proper system performance. The names of the critical
registers, their location, and brief description are listed below.
1. B0:D31:F0 Offset D5h (BACK_CNTL – Backed Up Control register) bits [7:6] need to be set to 1
in order to enable the tri-stating of the primary and secondary IDE pins when the interfaces are put
into reset. By default both bits are set to 1.
2. B0:D31:F0 Offset D0-D3h (GEN_CNTL – General Control register) bit [3] should be set to 1 in
order to lock the state of bits [7:6] at B0:D31:F0 Offset D5h. This prevents any inadvertent
reprogramming of the IDE interface pins to a non-tri-state mode during reset by a rogue software
program. By default this bit is set to 0 and BIOS should set this bit to 1. This is a write once bit
only and requires a PCIRST# to reset to 0. Thus, this bit also needs to be set to 1 after resume
from S3-S5.
3. B0:D31:F1 Offset 54h (IDE_CONFIG – IDE I/O Configuration register) bits [19:18]
(SEC_SIG_MODE) and bits [17:16] (PRIM_SIG_MODE) control the reset states of the
secondary and primary IDE channels, respectively. The values in SEC_SIG_MODE and
PRIM_SIG_MODE are tied to the values set by the BACK_CNTRL register bits [7:6],
respectively. When bits [7:6] are set to 1, the PRIM_SIG_MODE and SEC_SIG_MODE will be
set to 01 for tri-state when the either IDE channel is put in reset.
4. B0:D31:F1 Offset 40-41h (Primary) and 42-23h (Secondary) bit [5] and bit [1] (IDE_TIM – IDE
Timing register) are the IORDY Sample Point Enable bits for drive 1 and 0 of the primary and
secondary IDE channels, respectively. By default, these bits are set to 0 and during normal power
up, should be set to 1 by the BIOS to enable IORDY assertion from the IDE device when an
access is requested.
®
®
Intel
852GME, Intel
852GMV and Intel
®
852PM Chipset Platforms Design Guide
I/O Subsystem
151
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