Clearing The Ocxref Signal On An External Event; Figure 115. Clearing Timx Ocxref - ST STM32F412 Reference Manual

RM0402
16.3.13

Clearing the OCxREF signal on an external event

The OCxREF signal for a given channel can be driven Low by applying a High level to the
ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to '1'). The
OCxREF signal remains Low until the next update event, UEV, occurs.
This function can only be used in output compare and PWM modes, and does not work in
forced mode.
For example, the ETR signal can be connected to the output of a comparator to be used for
current handling. In this case, the ETR must be configured as follow:
1. The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR
register set to '00'.
2. The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to
'0'.
3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be
configured according to the user needs.
Figure 115
for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in
PWM mode.
OCxREF (OCxCE = '0')
OCxREF (OCxCE = '1')
Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at
the next counter overflow.
shows the behavior of the OCxREF signal when the ETRF Input becomes High,

Figure 115. Clearing TIMx OCxREF

(CCRx)
Counter (CNT)
ETRF
ETRF becomes high
RM0402 Rev 6
Advanced-control timers (TIM1&TIM8)
ETRF still high
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