Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1823

DMA Destination Address Low Read Channel Register
The
PCIE_DMARD_DAR_LO_[n]
on. All fields marked "Reserved" MUST be programmed to 1'b0. This register is not affected by any of the reset
signals.
VALUE[31:16] (R/W)
Lower 32 bits
Figure 29-45: PCIE_DMARD_DAR_LO_[n] Register Diagram
Table 29-54: PCIE_DMARD_DAR_LO_[n] Register Fields
Bit No.
(Access)
31:0 VALUE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register is implemented in RAM whose contents are uninitialized after power-
15
0
VALUE[15:0] (R/W)
Lower 32 bits
31
0
Bit Name
Lower 32 bits.
The PCIE_DMARD_DAR_LO_[n].VALUE bit field indicates the next address to be
written to. The DMA increments the DAR as the DMA transfer progresses. The DAR
is always dword aligned even if the transfer size is byte aligned. In LL mode, the DMA
overwrites this bit field with the corresponding dword of the LL element. he DAR is
the address of the local memory.
14 13 12 11 10 9 8 7
0 0 0 0 0 0 0 0
30 29 28 27 26 25 24 23
0 0 0 0 0 0 0 0
Description/Enumeration
ADSP-SC58x PCIE Register Descriptions
6 5 4 3 2 1 0
0 0 0 0 0 0 0
22 21 20 19 18 17 16
0 0 0 0 0 0 0
29–119