Timx Dma/Interrupt Enable Register (Timx_Dier)(X = 16 To 17) - ST STM32WL5 Series Reference Manual

General-purpose timers (TIM16/TIM17)
Bit 0 CCPC: Capture/compare preloaded control
0: CCxE, CCxNE and OCxM bits are not preloaded
1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated
Note: This bit acts only on channels that have a complementary output.
27.4.3

TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17)

Address offset: 0x0C
Reset value: 0x0000
15 14 13
Res. Res. Res.
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled
1: Update DMA request enabled
Bit 7 BIE: Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
Bit 6 Reserved, must be kept at reset value.
Bit 5 COMIE: COM interrupt enable
0: COM interrupt disabled
1: COM interrupt enabled
Bits 4:2 Reserved, must be kept at reset value.
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled
932/1461
only when COM bit is set.
12 11 10 9
Res. Res. Res. CC1DE
rw
8 7 6
UDE BIE Res. COMIE
rw rw
RM0453 Rev 1
5 4 3 2
Res. Res. Res.
rw
RM0453
1 0
CC1IE UIE
rw rw