Class Profiling Irq Enable Register (Cnpier); Class Profiling Reference Counter Register (Cnprcr) - Freescale Semiconductor MSC8144E Reference Manual

Chip-Level Arbitration and Switching System (CLASS)
4.7.21

CLASS Profiling IRQ Enable Register (CnPIER)

C0PIER
C1PIER
C2PIER
Bit 31 30 29
Type
Reset 0 0 0
Bit 15 14 13
Type
Reset 0 0 0
CnPIER enables/disables the generation of interrupts by the debug profiling unit. You can write
to the register at any time. The register is only reset by a hardware reset or by setting the
appropriate CnCPCR[PE] bit. Table 4-24 lists the CnPIER bit field descriptions.
Name Reset
— 0 Reserved. Write to 0 for future compatibility.
31–2
WPEE 0 Watch Point Event Enable
1 Enables/disables a watch point interrupt.
OVEE 0 Overflow Event Enable
0 Enables/disables an overflow interrupt.
4.7.22

CLASS Profiling Reference Counter Register (CnPRCR)

C0PRCR
C1PRCR
C2PRCR
Bit 31 30 29
Type
Reset 0 0 0
Bit 15 14 13
Type
Reset 0 0 0
4-42
CLASS Profiling IRQ Enable Registers
28 27 26 25
0 0 0 0
12 11 10 9
—
0 0 0 0
Table 4-24. CnPIER Bit Descriptions
Description
CLASS Profiling Reference Counter Registers
28 27 26 25
0 0 0 0
12 11 10 9
0 0 0 0
MSC8144E Reference Manual, Rev. 3
24 23 22 21
—
R/W
0 0 0 0
8 7 6 5
R/W
0 0 0 0
0 Watch point interrupt is masked.
1 Watch point interrupt is enabled.
0 Overflow interrupt is masked.
1 Overflow interrupt is enabled.
24 23 22 21
CNT
R
0 0 0 0
8 7 6 5
CNT
R
0 0 0 0
Offset 0xE24
20 19 18 17
0 0 0 0
4 3 2 1
WPEE OVEE
0 0 0 0
Settings
Offset 0xE40
20 19 18 17
0 0 0 0
4 3 2 1
0 0 0 0
Freescale Semiconductor
16
0
0
0
16
0
0
0