Rx And Tx Fifo Counter Register (Pscrfcntn, Psctfcntn); Rx And Tx Fifo Data Register (Pscrfdrn, Psctfdrn) - Freescale Semiconductor MCF5480 Reference Manual

Bits Name
7–4 —
3–0 F_FDIV

26.3.3.21 Rx and Tx FIFO Counter Register (PSCRFCNTn, PSCTFCNTn)

This register applies to all modes.
15 14 13
R 0 0 0
W
Reset 0 0 0
Reg MBAR + 0x8658 (PSCRFCNT0); 0x8758 (PSCRFCNT1); 0x8858 (PSCRFCNT2); 0x8958 (PSCRFCNT3)
Addr and MBAR + 0x865C (PSCTFCNT0); 0x875C (PSCTFCNT1); 0x885C (PSCTFCNT2); 0x895C (PSCTFCNT3)
Figure 26-18. RxFIFO (PSCRFCNTn) and TxFIFO (PSCTFCNTn) Counter Register
Table 26-29. PSCRFCNTn and PSCTFCNTn Field Descriptions
Bits Name
15-9 —
8–0 CNT

26.3.3.22 Rx and Tx FIFO Data Register (PSCRFDRn, PSCTFDRn)

These registers provide access to the internal Rx and Tx FIFOs.
Freescale Semiconductor
Table 26-27. PSCIRFDRn Field Descriptions
Reserved, should be cleared.
Applies only in FIR mode; in all other modes, this field is reserved.
In FIR mode, this field signifies clock divide ratio.
The bit frequency is derived by the following equation.
This bit frequency should be 8 MHz. In order to receive the minimum pulse width described in the
IrDA spec, (F_FDIV + 1) should be larger than or equal to 4. shows several frequency selection.
See Table 26-28., "Frequency Selection in FIR Mode
Table 26-28. Frequency Selection in FIR Mode
F_FDIV[3:0]
3
4
5
6
...
12 11 10 9
0 0 0 0
0 0 0 0
Reserved, should be cleared.
Number of bytes in the FIFO
MCF548x Reference Manual, Rev. 3
Description
f
bit_clk
f =
----------------------------- -
bit
F_FDIV + 1
Frequency of bit_clk [MHz]
32.0
40.0
48.0
56.0
...
8 7 6 5
0 0 0 0
Description
Memory Map/Register Definition
Eqn. 26-2
4 3 2 1
CNT
0 0 0 0
0
0
26-27