Sata Interfaces; Ahci Mode - Intel Atom N2800 User Manual

Embedded Intel® Atom™ Processor N2800 with Intel® NM10 Express Chipset Development Kit User's Manual
2.9

SATA Interfaces

The Kit provides two SATA ports through the Intel® NM10 Express Chipset PCH
(Platform Controller Hub), which supports one device per port:
 One internal SATA connector (black)
 One internal SATA connector (multiplexed with mSATA port, routed to PCI Express
Full-/Half-Mini Card slot) (gray)
The PCH provides independent SATA ports with a theoretical maximum transfer rate of
3 Gb/s. A point-to-point interface is used for host to device connections.
The underlying SATA functionality is transparent to the operating system. The SATA
controller can operate in both legacy and native modes. In legacy mode, standard IDE
I/O and IRQ resources are assigned (IRQ 14 and 15). In Native mode, standard PCI
Conventional bus resource steering is used. Native mode is the preferred mode for
configurations using Windows operating systems.
The board has an internal SATA power connector and ships with a power cable for
powering internal SATA storage devices. The power cable includes:
 Right-angled 15-pin SATA female connector (for motherboard connectivity)
 1 x 4 Molex female connector (for slim optical drive adapter connectivity)
 15-pin SATA female connector (for storage connectivity)
 Vertical 15-pin SATA female connector (for storage connectivity)

NOTE
Board power supplied through the SATA power connector is rated at a maximum of:
 1.0 A from 12 V rail
 2.5 A from 5 V rail
 0.5 A from 3.3 V rail
For information about
The location of the SATA connectors
2.9.1

AHCI Mode

The board supports AHCI storage mode via the Intel NM10 Express Chipset.

NOTE
In order to use AHCI mode, AHCI must be enabled in the BIOS. Microsoft Windows 7
includes the necessary AHCI drivers without the need to install separate AHCI drivers
during the operating system installation process, however, it is always good practice to
update the AHCI drivers to the latest available release.
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Refer to
Figure 13