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E
•
Stores can be constrained from passing loads,
for an inconsequential performance loss.
•
Constraining loads from passing other loads or
stores has a significant impact on performance.
The Memory Order Buffer (MOB) allows loads to
pass other loads and stores by acting like a
reservation station and re-order buffer. It holds
suspended loads and stores and re-dispatches them
when a blocking condition (dependency or resource)
disappears.
2.3.
Architecture Summary
Dynamic Execution is this combination of improved
branch prediction, speculative execution and data
flow analysis that enables the Pentium Pro processor
to deliver its superior performance.
3.0.
ELECTRICAL SPECIFICATIONS
3.1.
The Pentium
Bus and V
REF
Most of the Pentium Pro processor signals use a
variation of the low voltage Gunning Transceiver
Logic (GTL) signaling technology.
The Pentium Pro processor bus specification is
similar to the GTL specification but has been
enhanced to provide larger noise margins and
reduced ringing. This is accomplished by increasing
the termination voltage level and controlling the edge
rates. Because this specification is different from the
standard GTL specification, it is refered to as GTL+
in this document.
The GTL+ signals are open-drain and require
external termination to a supply that provides the
high signal level. The GTL+ inputs use differential
receivers which require a reference signal (V
Termination (usually a resistor on each end of the
signal trace) is used to pull the bus up to the high
voltage level and to control reflections on the stub-
free transmission line. V
REF
to determine if a signal is a logical 0 or a logical 1.
See Table 8 for the bus termination voltage
specifications for GTL+, and Section 4 for the GTL+
Interface Specification.
PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz
®
Pro Processor
).
REF
is used by the receivers
There are 8 V
pins on the Pentium Pro processor
REF
to ensure that internal noise will not affect the per-
formance of the I/O buffers. Pins A1, C7, S7 and Y7
(V
[3:0]) must be tied together and pins A47, U41,
REF
AE47 and AG45 (V
[7:4]) must be tied together.
REF
The two groups may also be tied to each other if
desired.
1.5V
No stubs
CPU
CPU
ASIC
Figure 7. GTL+ Bus Topology
The GTL+ bus depends on incident wave switching.
Therefore timing calculations for GTL+ signals are
based on flight time as opposed to capacitive
deratings. Analog signal simulation of the Pentium
Pro processor bus including trace lengths is highly
recommended when designing a system with a
heavily loaded GTL+ bus. See Intel's world wide web
page (http:\\www.intel.com) to download the buffer
models for the Pentium Pro processor in IBIS format.
3.2.
Power Management: Stop
Grant and Auto HALT
The Pentium Pro processor allows the use of Stop
Grant and Auto HALT modes to immediately reduce
the power consumed by the device. When enabled,
these cause the clock to be stopped to most of the
CPU's internal units and thus significantly reduces
power consumption by the CPU as a whole.
Stop Grant is entered by asserting the STPCLK# pin
of the Pentium Pro processor. When STPCLK# is
recognized by the Pentium Pro processor, it will stop
execution and will not service interrupts. It will contin-
ue snooping the bus. Stop Grant power is specified
assuming no snoop hits occur.
Auto HALT is a low-power state entered when the
Pentium Pro processor executes a halt (HLT)
instruction. In this state, the Pentium Pro processor
behaves as if it executed a halt instruction, and it
additionally powers-down most internal units. In Auto
1.5V
CPU
CPU
ASIC
11
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