Aes Registers; Aes Control Register (Aes_Cr) - ST STM32F423 Reference Manual

RM0430
Note: Data insertion can include wait states forced by AES on the AHB bus (maximum 3 cycles,
typical 1 cycle). This applies to all header/payload/tag phases.
24.7

AES registers

24.7.1

AES control register (AES_CR)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
DMAO
Res. GCMPH[1:0]
UTEN
rw rw
Bits 31:19 Reserved, must be kept at zero
Bit 18 KEYSIZE: Key size selection
This bitfield defines the length of the key used in the AES cryptographic core, in bits:
0: 128
1: 256
The bit value change is allowed only when AES is disabled, so as to avoid an unpredictable
behavior.
Bit 17 Reserved, must be kept at zero
Bit 16 CHMOD[2]: Chaining mode selection, bit [2]
Refer to the bits [5:6] of the register for the description of the CHMOD[2:0] bitfield
Bit 15 Reserved, must be kept at zero
Bits 14:13 GCMPH[1:0]: GCM or CCM phase selection
This bitfield selects the phase of GCM, GMAC or CCM algorithm:
00: Init phase
01: Header phase
10: Payload phase
11: Final phase
The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the
ALGOMODE bitfield).
28 27 26 25
Res. Res. Res.
12 11 10 9
DMAIN
ERRIE CCFIE
EN
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
ERRC CCFC CHMOD[1:0]
rw rw rw
RM0430 Rev 8
AES hardware accelerator (AES)
21 20 19 18
KEYSI
Res. Res. Res.
ZE
rw
5 4 3 2
MODE[1:0] DATATYPE[1:0]
rw rw rw rw
17 16
CHMO
Res.
D[2]
rw
1 0
EN
rw rw
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