Internal Interrupts - Hitachi H8/3035 Series Hardware Manual

IRQn
input
Note: n = 0 to 4
Figure 5-2 Block Diagram of Interrupts IRQ
Figure 5-3 shows the timing of the setting of the interrupt flags (IRQnF).
ø
IRQn
input pin
IRQnF
Note: n = 0 to 4
Interrupts IRQ to IRQ
0 4
of whether the corresponding pin is set for input or output. When using a pin for external
interrupt input, clear its DDR bit to 0 and do not use the pin for SCI input or output.

5.3.2 Internal Interrupts

Twenty-one internal interrupts are requested from the on-chip supporting modules.
• Each on-chip supporting module has status flags for indicating interrupt status, and enable
bits for enabling or disabling interrupts.
• Interrupt priority levels can be assigned in IPRA and IPRB.
82
IRQnSC
Edge/level
sense circuit
Clear signal
Figure 5-3 Timing of Setting of IRQnF
have vector numbers 12 to 16. These interrupts are detected regardless
IRQnE
IRQnF
S Q
R
to IRQ
0 4
IRQn interrupt
request