Internal Block Diagram - Hitachi H8/3006 Hardware Manual

1.2

Internal Block Diagram

Figure 1-1 shows an internal block diagram.
MD
2
MD
1
MD
0
EXTAL
XTAL
STBY
RES
RESO
NMI
AS
RD
HWR
LWR
φ/P6
7
BACK/P6
2
BREQ/P6
1
WAIT/P6
0
CS
/P8
0 4
ADTRG/CS
/IRQ /P8
1 3 3
CS
/IRQ /P8
2 2 2
CS
/IRQ /P8
3 1 1
RFSH/IRQ
/P8
0 0
H8/300H CPU
Interrupt controller
RAM
16-bit timer unit
8-bit timer unit
Programmable
timing pattern
controller (TPC)
Port B Port A
Figure 1-1 Block Diagram
Data bus Port 4
Address bus
Data bus (upper)
Data bus (lower)
DMA controller
(DMAC)
Watchdog timer
(WDT)
Serial communication
interface
×
(SCI) 3 channels
A/D converter
D/A converter
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
P9 /SCK /IRQ
5
P9 /SCK /IRQ
4
P9 /RxD
3
P9 /RxD
2
P9 /TxD
1
P9 /TxD
0
Port 7
1 5
0 4
1
0
1
0
5