ST STM32F101 series Reference Manual page 1106

RM0008
Date Revision
22-May-
4
2008
continued
continued
28-Jul-2008 5
Table 235. Document revision history (continued)
Figure 234: CAN frames on page 663
TX mailbox identifier register (CAN_TIxR) (x=0..2) on page
modified in CAN receive FIFO mailbox identifier register (CAN_RIxR) (x=0..1) on
page 679.
Section 26.3.7: DMA requests on page 761
modified in Section 26.6.2: I2C Control register 2 (I2C_CR2) on page
Clock phase and clock polarity on page 695
modified. Receive sequence on page 698
modified. Underrun flag (UDR) on page 731
2
I S feature added (see Section 25: Serial peripheral interface (SPI) on page
In Section 31: Debug support (DBG) on page
– DBGMCU_IDCODE on page 1076
– TMC TAP changed to boundary scan TAP
– Address onto which DBGMCU_CR is mapped modified in
MCU configuration register on page
Section 30: Device electronic signature on page 1065
REV_ID(15:0) definition modified in
Developed polynomial form updated in
Figure 4: Power supply overview on page 68
Section 5.1.2: Battery backup domain on page 69
Section 7.2.5: LSI clock on page 96
Section 9.1.4: Alternate functions (AF) on page 162
Note added to Table 45: TIM2 alternate function remapping on page
Bits are write-only in Section 13.4.2: DMA interrupt flag clear register (DMA_IFCR) on
page 285.
Register name modified in
Recommended sampling time given in
Bit attributes modified in
Note modified for bits 23:0 in
(ADC_SMPR1) on page
Note added in Section 12.2: DAC main features on page
Formula updated in Section 12.3.5: DAC output voltage on page
DBL[4:0] description modified in
synchronization on page
Figure 82 on page 312 and
Section 25.5.3: SPI status register (SPI_SR) on page 736
Closing the communication on page 753
Notes added to Section 26.6.8: I2C Clock control register (I2C_CCR) on page
replaced by T in Section 26.6.8
PCLK1
OVR changed to ORE in
Section 27.6.1: Status register (USART_SR) on page 811
Slave select (NSS) pin management on page 694
Small text changes.
DocID13902 Rev 15
Changes
modified. Bits 31:21 and bits 20:3 modified in
modified. DMAEN bit 11 description
modified.
added.
modified.
1068:
and DBGMCU_CR register on page 1091
1091.
Section 31.6.1: MCU device ID code on page
Section 4.2: CRC main features on page
modified.
specified.
Section 11.3.1: ADC on-off control on page
Section 11.10: Temperature sensor on page
Section 11.12.1: ADC status register (ADC_SR) on page
Section 11.12.4: ADC sample time register 1
243.
Section 14.3.19: TIMx and external trigger
329.
Figure 128 on page 378
updated.
and Section
Figure 301: USART interrupt mapping diagram on page
Revision history
676. Bits 31:21 and bits 20:3
767.
Transmit sequence on page 697
Reception sequence on page 730
Section 31.16.3: Debug
added.
modified.
clarified.
179.
218.
253.
257.
modified.
modified.
26.6.9.
updated.
clarified.
CAN
690).
updated
1076.
64.
234.
236.
775. TCK
810.
1106/1128
1120