Figure 360. Block Diagram Of Stm32 Mcu And Cortex ® -M3-Level - ST STM32F101 series Reference Manual

RM0008
Date Revision
22-Jun-
9
2009
Table 235. Document revision history (continued)
Reference manual updated to support also STM32F105xx/STM32F107xx connectivity
line devices.
Memory and bus architecture
Section 4.3: CRC functional description
Note modified in Section 5.1.2: Battery backup
Connectivity line devices: reset and clock control (RCC)
diagram of the reset circuit
description in Section 5.4.1: Power control register
remapping corrected.
DMA section: Table 76: Programmable data width & endian behavior (when bits PINC =
MINC = 1) updated, Section 13.3.1: DMA transactions
page 276 modified. DMA channel x peripheral address register (DMA_CPARx) (x =
1..7), where x = channel number)
(DMA_CMARx) (x = 1..7), where x = channel number)
channel is enabled.
Advanced-control timer section:
updated. BKE and BKP bit descriptions updated in
and dead-time register (TIMx_BDTR). CC1IF bit description modified in
TIM1&TIM8 status register (TIMx_SR)
(TIMx_SR).
Note added to Table 82: TIMx Internal trigger connection
trigger connection on page
Table 108: NOR Flash/PSRAM controller: example of supported memories and
transactions on page 507
Register numbering and address offset corrected in
register (SDIO_RESPx) on page
In Section 24: Controller area network
modified, small text changes.
SPI section: note added in
management clarified. Note added at the end of
master mode and Section 25.3.4: Configuring the SPI for half-duplex
Audio frequency precision tables
on page 722 and audio sampling frequency range increased to 96 kHz.
Arbitration lost (ARLO) on page 758
USART section: Description of "1.5 stop bits" updated in
flow control corrected. Procedure sequence modified in
How to derive USARTDIV from USART_BRR register values
USART receiver's tolerance to clock deviation
Section 27.3.10: Single-wire half-duplex communication
modified in Section 27.6.4: Control register 1
Debug support (DBG) section:
– Figure 360: Block diagram of STM32 MCU and Cortex®-M3-level debug support
updated
– Section 31.15: ETM (Embedded trace macrocell)
– Figure 363: TPIU block diagram
– in DBGMCU_IDCODE, REV_ID(15:0) updated for connectivity line devices (revision Z
added).
Section 28: USB on-the-go full-speed (OTG_FS)
DocID13902 Rev 15
Changes
section: Embedded boot loader
updated.
domain.
updated. PLL1 changed to PLL. Note added to BDP bit
and DMA channel x memory address register
Section 14.3.12: Using the break function on page 318
and Section 15.4.5: TIMx status register
401.
and Single-burst transfer
646.
(bxCAN): DBF bit reset value and access type
Section 25.2.2: I2S features.
Section 25.3.3: Configuring the SPI in
184 and 185 added to
specified.
added.
(USART_CR1).
updated
revised. Small text changes.
Revision history
updated.
section: Figure 10: Simplified
(PWR_CR). Table 57: SPI3/I2S3
and Pointer incrementation on
must not be written when the
Section 14.4.18: TIM1&TIM8 break
Section 14.4.5:
and Table 86: TIMx Internal
modified.
Section 1.9.6: SDIO response 1..4
Slave select (NSS) pin
communication.
Section 25.4.3: Clock generator
Configurable stop
Section 27.3.2: Transmitter.
modified. Section 27.3.5:
Section 27.3.11: Smartcard
updated. Bit 12 description
added
bits, RTS
and
1110/1128
1120