ST STM32F101 series Reference Manual page 1119

Revision history
Date Revision
02-Jun- 15
2014 (continued)
1119/1128
Table 235. Document revision history (continued)
FSMC:
Updated Figure 185: FSMC block
Updated Table 109 to Table
Replaced all occurrences of DATALAT by DATLAT in the whole section. Updated
Section 21.1: FSMC main
whole section.
Updated Section 21.5.3: General timing rules/Signals
– Updated Section 21.5.4: NOR Flash/PSRAM controller asynchronous transactions
– Modified step b) in Section 21.3.1: Supported memories and
– Moved note from Figure 188: Mode1 write accesses
accesses.
– Moved note from Figure 190: ModeA write accesses
accesses. Updated Section : WAIT management in asynchronous accesses
Figure 199: Asynchronous wait during a read
– Modified differences between Mode B and mode 1 in
– Modified differences between Mode C and mode 1 in
OE toggling.
– Modified differences between Mode D and mode 1 in
asynchronous access with extended
– Updated NWAIT signal in
Figure 200: Asynchronous wait during a write
Figure 202: Synchronous multiplexed read mode - NOR, PSRAM
Figure 203: Synchronous multiplexed write mode - PSRAM
Updated case of synchronous accesses in
Added register access in
Section 21.6.8: NAND Flash/PC Card control
Updated step3 of Section 21.6.4: NAND Flash
to non 'CE don't care' NAND-Flash
Updated Section 21.6.6: Computation of the error correction code (ECC) in NAND Flash
memory.
Updated access to I/O Space in
Updated Table 132: 16-bit PC
Changed bits 16 to 19 to BUSTURN in
1..4 (FSMC_BWTR1..4). Updated BUSTURN bit definition in
Flash chip-select timing registers 1..4
Flash chip-select control registers 1..4
Updated definition of PWID in
(FSMC_PCR2..4).
DocID13902 Rev 15
Changes
diagram.
128.
features. Replace SRAM/CRAM by SRAM/PSRAM in the
access.
address.
Figure 199: Asynchronous wait during a read
access,
Section 21.5: NOR Flash/PSRAM
Section 21.5.6: NOR/PSRAM control registers
registers.
operations, updated
and note below.
Section 21.6.7: PC Card/CompactFlash
Card.
Section : SRAM/NOR-Flash write timing registers
(FSMC_BTR1..4). Updated
(FSMC_BCR1..4).
Section : PC Card/NAND Flash control registers 2..4
synchronization.
transactions.
to Figure 187: Mode1 read
to Figure 189: ModeA read
Section : Mode 2/B - NOR
Section : Mode C - NOR Flash -
Section : Mode D -
access,
Figure 201: Wait configurations,
(CRAM), and
(CRAM).
controller.
and
Figure 205: Access
operations.
Section : SRAM/NOR-
Section : SRAM/NOR-
RM0008
and
Flash.