ST STM32F101 series Reference Manual page 1109

Revision history
Date Revision
11-Feb-
8
2009
1109/1128
Table 235. Document revision history (continued)
Reset value corrected in
Section 11.10: Temperature sensor
ADC watchdog high threshold register
Section 12.3.9: Triangle-wave generation
updated.
Section 24.6: Debug mode
(CAN_MCR) on page 665.
Note added to Section 25.3.6: CRC
Changes concerning the I
– In Slave transmitter on page
diagram for slave transmitter
– In Slave receiver on page
diagram for slave receiver
– Master transmitter on page 751
– In Closing the communication on page
sequence diagram for master transmitter
– Figure 273: Method 1: transfer sequence diagram for master receiver
– Overrun/underrun error (OVR) on page 758
– Section 26.3.7: DMA requests
– In Section 26.6.1: I2C Control register 1
and notes modified under POS bit.
– Receiver mode modified in DR bit description in
(I2C_DR).
– Note added to TxE and RxNE bit descriptions in
(I2C_SR1).
Changes in FSMC section:
– Data setup and Address hold min values corrected in
NOR/PSRAM access
– Memory wait min value corrected in
parameters.
– Bit descriptions modified in
(FSMC_BTR1..4) on page
– DATAST and ADDHLD are reserved when equal to 0x0000 in
select timing registers 1..4 (FSMC_BTR1..4) on page 535
write timing registers 1..4 (FSMC_BWTR1..4) on page
– Bit descriptions modified in
(FSMC_PMEM2..4)
– ATTHOLDx and ATTWAITx bit descriptions modified in
registers 2..4 (FSMC_PATT2..4)
– IOHOLDx bit description modified in
DocID13902 Rev 15
Changes
Section 4.4.1: Data register
modified. Reset value corrected in
(ADC_HTR).
and Figure 46: DAC triangle wave generation
added. Bit 16 updated in
calculation.
2
C peripheral (Inter-integrated circuit (I2C)
747: text changes and
modified.
748: text changes and
modified.
and Master receiver on page 753
751: text changes and
modified.
clarified.
and Section 26.3.8: Packet error checking
(I2C_CR1): note modified under STOP bit
parameters.
Table 129: Programmable NAND/PC Card access
SRAM/NOR-Flash chip-select timing registers 1..4
535.
Common memory space timing register 2..4
I/O space timing register 4 (FSMC_PIO4)
(CRC_DR).
Section 11.12.7:
CAN master control register
interface):
Figure 270: Transfer sequence
Figure 271: Transfer sequence
clarified.
Figure 272: Transfer
modified.
Section 26.6.5: I2C Data register
Section 26.6.6: I2C Status register 1
Table 104: Programmable
SRAM/NOR-Flash chip-
and SRAM/NOR-Flash
537.
Attribute memory space timing
RM0008
updated.