ST STM32F101 series Reference Manual page 1117

Revision history
Date Revision
02-Jun-
15
2014
1117/1128
Table 235. Document revision history (continued)
Updated Table 3: Register boundary addresses
Restricted hyperlinks to homepages.
PWR:
Added note related to HSE failure in
to Stop mode entry in Table 14: Stop
Section 5.4.2: Power control/status register
Low-, medium-, high- and XL-density RCC:
Updated Figure 7: Simplified diagram of the reset
Connectivity line RCC:
Updated Figure 10: Simplified diagram of the reset
Interrupts and events:
Updated bit definitions in
(EXTI_SWIER) and Section 10.3.6: Pending register
ADC:
Updated examples in Section 11.3.10: Discontinuous mode
Updated note related to prerequisites to start calibration in
Updated note related to sampling time in
Section 11.9.2: Regular simultaneous
simultaneous mode, and
trigger mode.
TIMER1/8:
Updated 16-bit prescaler range in
Modified update event generation in
Section 14.3.2: Counter
Updated OC1 block diagram in
(channel 1 to 3). Updated
Updated bits that control the dead-time generation in
Complementary outputs and dead-time
Updated ways to generate a break in
OCxREF changed to ETR in the example given in
OCxREF signal on an external event
TIMx OCxREF
.
Updated configuration for example of counter operation in encoder interface mode in
Section 14.3.16: Encoder interface
Updated Section 14.3.18: Interfacing with Hall
Updated CCPC definition in
Changed definition of ARR[15:0] bits in
register (TIMx_ARR).
Updated BKE definition in
(TIMx_BDTR).
DocID13902 Rev 15
Changes
Section : Entering Stop
mode. Changed conditions to clear CWUF in
(PWR_CSR).
Section 10.3.5: Software interrupt event register
Section 11.9.1: Injected simultaneous
mode, Section 11.9.7: Combined regular/injected
Section 11.9.8: Combined regular simultaneous + alternate
Section 14.2: TIM1&TIM8 main
Upcounting mode
modes, and in Section 14.3.3: Repetition
Figure 80: Output stage of capture/compare channel
Section 14.3.6: Input capture
insertion.
Section 14.3.12: Using the break
and OCREF_CLR to ETRF in
mode.
sensors.
Section 14.4.2: TIM1&TIM8 control register 2
Section 14.4.12: TIM1&TIM8 auto-reload
Section 14.4.18: TIM1&TIM8 break and dead-time register
mode. Updated note related
circuit.
circuit.
(EXTI_PR).
Section 11.4: Calibration.
features.
and Downcounting mode
counter.
mode.
Section 14.3.11:
function.
Section 14.3.13: Clearing the
Figure 90: Clearing
RM0008
mode,
in
(TIMx_CR2).