ST STM32F101 series Reference Manual page 1107

Revision history
Date Revision
26-Sep-
6
2008
1107/1128
Table 235. Document revision history (continued)
This reference manual also applies to low-density STM32F101xx, STM32F102xx and
STM32F103xx devices, and to medium-density STM32F102xx devices. In all sections,
definitions of low-density and medium-density devices updated.
Section 2.3: Peripheral availability on page 47
Section 3.3.3: Embedded Flash memory on page 55
backup domain on page 69
(GPIOx_IDR) (x=A..G) on page 172
on page 183. Note removed from bits 18:0 description in
register (EXTI_PR) on page
Section 14.2: TIM1&TIM8 main features on page 293
features on page 361 updated. In
TS=000.
FSMC_CLK signal direction corrected in
"Feedback clock" paragraph removed from
page 508.
In Section 21.5.6: NOR/PSRAM control registers on page
WAITEN bit default value after reset is 1, bits [5:6] definition modified, , FACCEN default
value after reset specified. NWE signal behavior corrected in
multiplexed write mode - PSRAM (CRAM) on page
support COSMO RAM and OneNAND devices, and it does not support the
asynchronous wait feature. SRAM and ROM 32 memory data size removed from
Table 108: NOR Flash/PSRAM controller: example of supported memories and
transactions on page 507.
Data latency versus NOR Flash latency on page 526
reserved in SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) on
page 537.
Section 21.6.3: Timing diagrams for NAND and PC Card on page 541
modified.Definition of PWID bits modified in
control registers on page
(ECC) in NAND Flash memory on page 544
Interrupt Mapper definition modified in
page 615. USB register and memory base addresses modified in
registers on page 628.
Section 26.3.8: Packet error checking on page 763
Section : Start bit detection on page 787
register (USART_SR) on page
"RAM size register" section removed from
page 1065. Bit definitions updated in
(FSMC_SR2..4) on page
Small text changes.
DocID13902 Rev 15
Changes
added.
modified. Reset value of
modified. Note added in
212.
Section 15.3.15: Timer synchronization on page
Figure 185: FSMC block diagram on page
Section 21.5.3: General timing rules on
Section 21.6.8: NAND Flash/PC Card
547. Section 21.6.6: Computation of the error correction code
modified.
Section 23.3.1: Description of USB blocks on
added. PE bit description specified in
811.
Section 30: Device electronic signature on
FIFO status and interrupt register 2..4
548.
updated. Section 5.1.2: Battery
Port input data register
Section 9.4: AFIO registers
Section 10.3.6: Pending
and Section 15.2: TIMx main
532: reset value modified,
Figure 203: Synchronous
530. The FSMC interface does not
modified. Bits 19:16 bits are
Section 23.5: USB
modified.
RM0008
391,
500.
Status