ST STM32F101 series Reference Manual page 1112

RM0008
Date Revision
04-Dec- 10
2009 continued
Table 235. Document revision history (continued)
TXFELVL bit description modified in
(OTG_FS_GAHBCFG).
NPTXFE bit description modified in
(OTG_FS_GINTSTS).
NPTXFEM bit description modified in
(OTG_FS_GINTMSK).
Figure 312: Transmit FIFO write task
Bit 22 is reserved in OTG_FS interrupt mask register
Bit 29 description modified in
(OTG_FS_DIEPCTLx) (x = 1..3, where x =
Bits 21:20 no longer reserved in
(OTG_FS_HCCHARx) (x = 0..7, where x =
There are only 4 IN and OUT endpoints:
– Bit descriptions corrected in
(OTG_FS_DAINTMSK).
– Bits 15:0 description corrected in
mask register: (OTG_FS_DIEPEMPMSK)
– Table 207: OTG_FS register map and reset values
Note added to Section 29.4: Ethernet functional description: SMI, MII and RMII on
page 962.
Note added to Unicast destination address filter
System consideration during power-down on page 993
Figure 326: ETH block diagram
Transmit descriptor Word0
control and status on page
Ethernet MAC hash table high register (ETH_MACHTHR)
Description of bits 6:2 modified in
Peripheral register access specified in
DocID13902 Rev 15
Changes
OTG_FS AHB configuration register
OTG_FS core interrupt register
OTG_FS interrupt mask register
modified.
OTG device endpoint-x control register
Endpoint_number).
OTG_FS Host channel-x characteristics register
Channel_number).
OTG_FS all endpoints interrupt mask register
OTG_FS device IN endpoint FIFO empty interrupt
(there are only 4 endpoints).
and
modified. CIC bit description modified in
and TDES0: Transmit descriptor Word0: Transmit time stamp
967.
Ethernet DMA bus mode register
Section 29.8: Ethernet register
Revision history
(OTG_FS_GINTMSK).
corrected
Multicast destination address
updated.
TDES0:
description clarified.
(ETH_DMABMR).
descriptions.
filter.
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