Revision History; Table 235. Document Revision History - ST STM32F101 series Reference Manual

Revision history

32 Revision history
Date Revision
19-Oct-2007 1
1101/1128

Table 235. Document revision history

Document reference number changed from UM0306 to RM0008. The changes below
were made with reference to revision 1 of 01-Jun-2007 of UM0306.
EXTSEL[2:0] and JEXTSEL[2:0] removed from
V range modified in Remarks column.
REF+
Notes added to Section 11.3.9 on page
on page 232 and Section 11.9.9 on page
SPI_CR2 corrected to SPI_CR1 in
on page 699.
f frequency changed to f
CPU
page 691.
Section 25.3.6: CRC calculation on page 706
using DMA (direct memory addressing) on page 710
Note added to bit 13 description changed in
(SPI_CR1) (not used in I2S mode) on page
Section 25.5.3: SPI status register (SPI_SR) on page
On 64-pin packages and packages with less pins on page 68
Section 9.3.2: Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 on page 175
updated.
Description of SRAM at address 0x4000 6000 modified in
page 39 and Table 3: Register boundary
Note added to Section 23.2: USB main features on page 613
main features on page 645.
Figure 4: Power supply overview
Formula added to Bits 25:24 description in
page 674.
Figure 49: DMA block diagram in low-, medium- high- and XL-density devices on
page 275 modified.
Example of configuration on page 1088
MODEx[1:0] bit definitions corrected in
(GPIOx_CRH) (x=A..G) on page
Downcounting mode on page 299
Figure 81: Output stage of capture/compare channel (channel 4) on page 310
Figure 83: Output compare mode, toggle on OC1.
conditions modified in Section 14.3.10: PWM mode on page
Section 14.3.19: TIMx and external trigger synchronization on page 329
CC1S, CC2S, CC3S and CC4S definitions modified for (1, 1) bit setting modified in
Section 14.4.7: TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1)
Section 14.4.8: TIM1&TIM8 capture/compare mode register 2
CC1S, CC2S, CC3S and CC4S definitions for (1, 1) bit setting modified in
Section 15.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1)
Section 15.4.8: TIMx capture/compare mode register 2
AFIO_EVCR pins modified in
page 194. Section 14.3.6: Input capture mode on page 310
DocID13902 Rev 15
Changes
Table 65: ADC pins on page 217
221, Section 11.9.2 on page
233.
1 clock and 1 bidirectional data wire (BIDIMODE=1)
in Section 25.2: SPI and I2S main features on
PCLK
and Section 25.3.9: SPI communication
Section 25.5.1: SPI control register 1
733. Note for bit 4 modified in
addresses.
and On 100-pin and 144-pin packages
CAN bit timing register (CAN_BTR) on
modified.
Section 9.2.2: Port configuration register high
172.
modified.
modified. OCx output enable
Table 60: AFIO register map and reset values on
229, Section 11.9.7
modified.
736.
modified.
Figure 2: Memory map on
and Section 24.2: bxCAN
modified.
314.
title changed.
(TIMx_CCMR2).
and
(TIMx_CCMR2).
modified.
RM0008
and
and
and