Xe000 - Samsung S5PC100 User Manual

S5PC100 USER'S MANUAL (REV1.0)
8 REGISTER DESCRIPTION
8.1 REGISTER OVERVIEW
Register Address
0XF210_0000
I2SCON
0XF220_0000
0XF210_0004
I2SMOD
0XF220_0004
0XF210_0008
I2SFIC
0XF220_0008
0XF210_000C
I2SPSR
0XF220_000C
0XF210_0010
I2STXD
0XF220_0010
0XF210_0014
I2SRXD
0XF220_0014
NOTE: All registers of I2S interface are accessible by word unit with STR/LDR instructions.
8.2 DETAILED DESCRIPTION
8.2.1 I2S interface control register (I2SCON, R/W, Address = 0XF210_0000, 0XF220_0000)
I2SCON1, R/W, Address = 0XF210_0000
I2SCON2, R/W, Address = 0XF220_0000
I2SCON
Reserved [31:20]
FRXOFSTATUS
FRXORINTEN
FTXURSTATUS
FTXURINTEN
Reserved [15:12]
Table 10.3-3 Register Summary of I2S Interface
R/W
R/W I2S Interface Control Register
R/W I2S Interface Mode Register
R/W I2S Interface FIFO Control Register
R/W I2S Interface Clock Divider Control Register
W I2S Interface Transmit Data Register
R I2S Interface Receive Data Register
Bit
Reserved
[19] RX FIFO OverFlow Interrupt Status.This is used by
interrupt clear bit. If this is high, write '1' to clear interrupt.
0 = Interrupt did not occurred.
1 = Interrupt occurred.
[18] RX FIFO OverFlow Interrupt Enable
0 = Disables RXFIFO Under-run INT
1 = Enables RXFIFO Under-run INT
[17] TX FIFO under-run interrupt status. This is used by
interrupt clear bit. If this is high, write '1' to clear the
interrupt.
0 = Interrupt did not occurred.
1 = Interrupt occurred.
[16] TX FIFO Under-run Interrupt Enable
0 = Disables TXFIFO Under-run INT
1 = Enables TXFIFO Under-run INT
Reserved
Description
Description
I2S CONTROLLER(2CH)
Reset Value
0xE00
0x0
0x0
0x0
0x0
0x0
R/W Reset
Value
R/W
R/W
R/W
R/W
R/W
R/W
10.3-13