Dma Round-Robin Priority Group Update Register (Dmarrpgur) - Freescale Semiconductor MSC8144E Reference Manual

Direct Memory Access (DMA) Controller
Table 14-26. DMALPCR Field Descriptions (Continued)
Bits Reset
CHAPRO 0
6–1
DEST 0
0

14.6.18 DMA Round-Robin Priority Group Update Register (DMARRPGUR)

DMARRPGUR
Bit 31 30 29
TYPE
RESET 0 0 0
Bit 15 14 13
—
TYPE
RESET 0 0 0
DMARRPGR is a special register that allows you to modify the DMACHCR[RRPG] bit without
a read-modify-write operation.
Note: Do not modify this register while the DMA controller is in EDF mode
(DMAGCR[AT] is set—see page 14-27).
Bits
— Reserved. Write to zero for future compatibility.
31–10
CH Channel Number
9–4 The channel number to which DMACHCR[RRPG] should be changed.
NRRPG New Channel Round-Robin Priority Group
3–1 The new value of RRPG to be written to the corresponding CHCR of
the channel.
EN Enable RRPG Update
0 Enables the RRPG update. Then the DMA controller clears this bit
14-40
Description
Channel Profiled
Selects the channel to be profiled.
Write by: User
Destination Channel Profiled
Specifies whether source or destination
requests are profiled.
Write by: User
DMA Round-Robin Priority Group Update Register
28 27 26 25
0 0 0 0
12 11 10 9
0 0 0 0
Table 14-27. DMARRPGUR Field Descriptions
Description
MSC8144E Reference Manual, Rev. 3
000000–001111: Channel number.
01xxxx Reserved.
10xxxx Reserved.
0 Channel source requests are
profiled.
1 Channel destination requests are
profiled.
24 23 22 21
—
R
0 0 0 0
8 7 6 5
CH
R/W
0 0 0 0
000000–001111: Channel number.
01xxxx Reserved.
1xxxxx Reserved.
000
...
011
1xx
Settings
Offset 0x37C
20 19 18 17
0 0 0 0
4 3 2 1
NRRPG
0 0 0 0
Settings
Highest priority.
Lowest priority.
Reserved.
Freescale Semiconductor
16
0
0
EN
0