Arbiter Master Priority Register (Xarb_Pri) - Freescale Semiconductor MCF5480 Reference Manual

Bits Name
31–4 —
3 M3
2 M2
1 —
0 M0
When enabled, the software programmable value in the arbiter master priority register (XARB_PRI) is
used as the priority for the master. When disabled, the master's priority is determined as follows:
Master Priority
M7–M4 —
M3 7
M2 7
M1 —
M0 7

10.3.3.11 Arbiter Master Priority Register (XARB_PRI)

The master n priority bits of the arbiter master priority register are used to set the priority of each master
if the corresponding arbiter master priority enable register bit is enabled. This XARB_PRI register, in
conjunction with the arbiter master priority enable (XARB_PRIEN) register, allows master priorities to be
set, ignoring the hardcoded priority. This register may be written at anytime. The change will become
effective 1 clock after the register is written. Valid values are from 0 to 7, with 0 being the highest priority.
31 30 29
R 0 Reserved
W
Reset 0 1 1
15 14 13
R 0 M3 Priority
W
Reset 0 1 1
Reg
Addr
Freescale Semiconductor
Table 10-14. XARB_PRIEN Field Descriptions
Reserved, should be cleared.
Master 3 Priority Register Enable
Master 2 Priority Register Enable
Reserved, should be cleared.
Master 0 Priority Register Enable
Table 10-15. Hardcoded Master Priority
Unused
PCI Target Interface
Multichannel DMA
Unused
ColdFire core
28 27 26 25
0 Reserved
1 0 1 1
12 11 10 9
0 M2 Priority
1 0 1 1
Figure 10-15. Arbiter Master Priority Register (XARB_PRI)
MCF548x Reference Manual, Rev. 3
Description
Description
24 23 22 21
0 Reserved
1 0 1 1
8 7 6 5
0 Reserved
1 0 1 1
MBAR + 0x0268
XL Bus Arbiter
20 19 18 17
0 Reserved
1 0 1 1
4 3 2 1
0 M0 Priority
1 0 1 1
16
1
0
1
10-17