Fec Transmit Fifo Watermark Register (Fectfwr) - Freescale Semiconductor MCF5480 Reference Manual

31 30
R
W
Reset
15 14
R
W
Reset
Reg
Addr
Bits Name
31–0 GADDR2

30.3.3.17 FEC Transmit FIFO Watermark Register (FECTFWR)

The FECTFWR is a 32-bit read/write register programmed by the user to control the amount of data
required in the transmit FIFO before transmission of a frame can begin. This allows the user to minimize
transmit latency or allow for larger bus access latency due to contention for the system bus. Setting the
watermark to a high value will minimize the risk of transmit FIFO underrun due to contention for the
system bus. The byte counts associated with the X_WMRK field may need to be modified to match a given
system requirement (worst case bus access latency by the transmit data DMA channel). This register
should be programmed so that the selected number of bytes is less than or equal to the number of bytes
indicated in the transmit FIFO alarm register, FECTFAR.
Both the transmit and receive FIFOs are 1024 bytes deep.
31 30 29
R 0 0 0
W
Reset 0 0 0
15 14 13
R 0 0 0
W
Reset 0 0 0
Reg
Addr
Figure 30-20. FEC Transmit FIFO Watermark Register (FECTFWR)
Freescale Semiconductor
29 28 27 26
13 12 11 10
MBAR + 0x9124 (FEC0), 0x9924 (FEC1)
Figure 30-19. Group Address Lower Register (GALR)
Table 30-23. GALR Field Descriptions
Group Address Lower - The GADDR2 register contains the lower 32 bits of the 64-bit hash
table used in the address recognition process for receive frames with a multicast address.
Bit 31 of GADDR2 contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0.
28 27 26 25
0 0 0 0
0 0 0 0
12 11 10 9
0 0 0 0
0 0 0 0
MBAR + 0x9144 (FEC0), 0x9944 (FEC1)
MCF548x Reference Manual, Rev. 3
25 24 23 22
GADDR2
Uninitialized
9 8 7 6
GADDR2
Uninitialized
Description
24 23 22 21
0 0 0 0
0 0 0 0
8 7 6 5
0 0 0 0
0 0 0 0
Memory Map/Register Definition
21 20 19 18
5 4 3 2
20 19 18
0 0 0
0 0 0
4 3 2
0 X_WMRK
0 0 0
17 16
1 0
17 16
0 0
0 0
1 0
0 0
30-25