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Address: 0xFC03_0084
31
30
29
R
0
0
0
W
Reset
0
0
0
15
14
13
R
0
0
0
W
Reset
0
0
0
Field
31–27
Reserved, must be cleared.
26–16
Maximum frame length. Resets to decimal 1518. Length is measured starting at DA and includes the CRC at the
MAX_FL
end of the frame. Transmit frames longer than MAX_FL causes the BABT interrupt to occur. Receive frames longer
than MAX_FL causes the BABR interrupt to occur and sets the LG bit in the end of frame receive buffer descriptor.
The recommended default value to be programmed is 1518 or 1522 if VLAN tags are supported.
15–6
Reserved, must be cleared.
5
Flow control enable. If asserted, the receiver detects PAUSE frames. Upon PAUSE frame detection, the transmitter
FCE
stops transmitting data frames for a given duration.
4
Broadcast frame reject. If asserted, frames with DA (destination address) equal to FFFF_FFFF_FFFF are rejected
BC_REJ
unless the PROM bit is set. If BC_REJ and PROM are set, frames with broadcast DA are accepted and the M
(MISS) is set in the receive buffer descriptor.
3
Promiscuous mode. All frames are accepted regardless of address matching.
PROM
2
Media independent interface mode. Selects the external interface mode for transmit and receive blocks.
MII_MODE
0 7-wire mode (used only for serial 10 Mbps)
1 MII mode
1
Disable receive on transmit.
DRT
0 Receive path operates independently of transmit (use for full duplex or to monitor transmit activity in half duplex
mode).
1 Disable reception of frames while transmitting (normally used for half duplex mode).
0
Internal loopback. If set, transmitted frames are looped back internal to the device and transmit output signals are
LOOP
not asserted. The internal bus clock substitutes for the FEC_TXCLK when LOOP is asserted. DRT must be set to
0 when setting LOOP.
19.4.11 Transmit Control Register (TCR)
TCR is read/write and configures the transmit block. This register is cleared at system reset. Bits 2 and 1
must be modified only when ECR[ETHER_EN] is cleared.
Freescale Semiconductor
28
27
26
25
0
0
0
0
1
0
12
11
10
9
0
0
0
0
0
0
0
0
Figure 19-10. Receive Control Register (RCR)
Table 19-14. RCR Field Descriptions
MCF5329 Reference Manual, Rev 3
24
23
22
21
MAX_FL
1
1
1
1
8
7
6
5
0
0
0
BC_
FCE
REJ
0
0
0
0
Description
Fast Ethernet Controller (FEC)
Access: User read/write
20
19
18
17
0
1
1
1
4
3
2
1
MII_
PROM
DRT LOOP
MODE
0
0
0
0
19-17
16
0
0
1
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