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Field
31–23
Reserved, must be cleared.
22
Receive DMA enable.
RDMAE
• If the Rx FIFO is enabled, a DMA request generates when either of the SSI_ISR[RFF0/1] bits is set.
• If the Rx FIFO is disabled, a DMA request generates when either of the SSI_ISR[RDR0/1] bits is set.
0 SSI receiver DMA requests disabled.
1 SSI receiver DMA requests enabled.
21
Receive interrupt enable. Allows the SSI to issue receiver related interrupts to the processor. Refer to
RIE
Section 25.4.5, "Receive Interrupt Enable Bit Description,"
0 SSI receiver interrupt requests disabled.
1 SSI receiver interrupt requests enabled.
20
Transmit DMA enable.
TDMAE
• If the Tx FIFO is enabled, a DMA request generates when either of the SSI_ISR[TFE0/1] bits is set.
• If the Tx FIFO is disabled, a DMA request generates when either of the SSI_ISR[TDE0/1] bits is set.
0 SSI transmitter DMA requests disabled.
1 SSI transmitter DMA requests enabled.
19
Transmit interrupt enable. Allows the SSI to issue transmitter data related interrupts to the core. Refer to
TIE
Section 25.4.6, "Transmit Interrupt Enable Bit Description,"
0 SSI transmitter interrupt requests disabled.
1 SSI transmitter interrupt requests enabled.
18–0
Controls if the corresponding status bit in SSI_ISR can issue an interrupt to the processor. See
"SSI Interrupt Status Register (SSI_ISR),"
0 Status bit cannot issue interrupt.
1 Status bit can issue interrupt.
25.3.10 SSI Transmit Configuration Register (SSI_TCR)
The SSI transmit configuration register directs the transmit operation of the SSI. A power-on reset clears
all SSI_TCR bits. However, an SSI reset does not affect the SSI_TCR bits.
Address: 0xFC0B_C01C (SSI_TCR)
31
30
29
R
0
0
W
Reset
0
0
15
14
13
R
0
0
W
Reset
0
0
Freescale Semiconductor
Table 25-9. SSI_IER Field Descriptions
28
27
26
0
0
0
0
0
0
0
0
12
11
10
0
0
0
0
0
0
0
0
Figure 25-17. SSI Transmit Configuration Register (SSI_TCR)
MCF52277 Reference Manual, Rev. 1
Description
for a detailed description of this bit.
for a detailed description of this bit.
for details on the individual bits.
25
24
23
22
0
0
0
0
0
0
0
0
9
8
7
6
TX
TFEN1 TFEN0 TFDIR TXDIR TSHFD TSCKP TFSI TFSL TEFS
BIT0
1
0
0
0
Synchronous Serial Interface (SSI)
Section 25.3.8,
Access: User read/write
21
20
19
18
0
0
0
0
0
0
0
0
5
4
3
2
0
0
0
0
17
16
0
0
0
0
1
0
0
0
25-21
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