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.
11
RDC2
23
RHCKD
Hardware and software reset clear all the bits of the RCCR register. The ESAI RCCR register is located at x:$FFFFB8. The ESAI_1 RCCR
register is located at y:$FFFF98.
8.3.3.1
RCCR Receiver Prescale Modulus Select (RPM7–RPM0) - Bits 7–0
The RPM7–RPM0 bits specify the divide ratio of the prescale divider in the ESAI receiver clock generator. A divide ratio from 1 to 256
(RPM[7:0]=$00 to $FF) may be selected. The bit clock output is available at the receiver serial bit clock (SCKR) pin of the DSP. The bit clock
output is also available internally for use as the bit clock to shift the receive shift registers. The ESAI receive clock generator functional
diagram is shown in
Figure
8-3.
8.3.3.2
RCCR Receiver Prescaler Range (RPSR) - Bit 8
The RPSR controls a fixed divide-by-eight prescaler in series with the variable prescaler. This bit is used to extend the range of the prescaler
for those cases where a slower bit clock is desired. When RPSR is set, the fixed prescaler is bypassed. When RPSR is cleared, the fixed
divide-by-eight prescaler is operational (see
internally generated bit clock frequency is Fosc/(2 x 8 x 256)=Fosc/4096.
Do not use the combination RPSR=1 and RPM7-RPM0=$00, which causes synchronization
problems when using the internal DSP clock as source (RHCKD=1 or RCKD=1).
8.3.3.3
RCCR Rx Frame Rate Divider Control (RDC4–RDC0) - Bits 13–9
The RDC4–RDC0 bits control the divide ratio for the programmable frame rate dividers used to generate the receiver frame clocks.
In network mode, this ratio may be interpreted as the number of words per frame minus one. The divide ratio may range from 2 to 32
(RDC[4:0]=00001 to 11111) for network mode. A divide ratio of one (RDC[4:0]=00000) in network mode is a special case (on-demand
mode).
In normal mode, this ratio determines the word transfer rate. The divide ratio may range from 1 to 32 (RDC[4:0]=00000 to 11111) for normal
mode. In normal mode, a divide ratio of one (RDC[4:0]=00000) provides continuous periodic data word transfers. A bit-length frame sync
(RFSL=1) must be used in this
case.
The ESAI frame sync generator functional diagram is shown in
8.3.3.4
RCCR Rx High Frequency Clock Divider (RFP3-RFP0) - Bits 17-14
The RFP3–RFP0 bits control the divide ratio of the receiver high frequency clock to the receiver serial bit clock when the source of the receiver
high frequency clock and the bit clock is the internal DSP clock. When the HCKR input is being driven from an external high frequency clock,
the RFP3-RFP0 bits specify an additional division ration in the clock divider chain. See
ESAI high frequency generator functional diagram is shown in
Freescale Semiconductor
10
9
8
7
RDC1
RDC0
RPSR
RPM7
22
21
20
19
RFSD
RCKD RHCKP RFSP
Figure 8-8. RCCR Register
Figure
8-3). The maximum internally generated bit clock frequency is Fosc/4, the minimum
NOTE
Figure
Figure
DSP56374 Users Guide, Rev. 1.2
6
5
4
3
RPM6
RPM5
RPM4
RPM3
18
17
16
15
RCKP
RFP3
RFP2
RFP1
8-4.
Table 8-6
for the specification of the divide ratio. The
8-3.
ESAI Programming Model
2
1
0
RPM2
RPM1
RPM0
14
13
12
RFP0
RDC4
RDC3
8-17
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