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Reads from the PSCRFDRn register return received data from the Rx FIFO. In addition, this register
provides the possibility to fill the Rx FIFO for software development/debug purposes.
Writes to the PSCTFDRn register write data into the Tx FIFO. In addition, this register provides the
possibility to read data back from the Tx FIFO for software development/debug purposes.
Refer to
Section 26.3.3.6, "Receiver Buffer (PSCRBn) and Transmitter Buffer
information about the data formats.
31
30
R
W
Reset
0
0
15
14
R
W
Reset
0
0
Reg
MBAR + 0x8660 (PSCRFDR0); 0x8760 (PSCRFDR1); 0x8860 (PSCRFDR2); 0x8960 (PSCRFDR3)
Addr
and MBAR + 0x8680 (PSCTFDR0); 0x8780 (PSCTFDR1); 0x8880 (PSCTFDR2); 0x8980 (PSCTFDR3)
Figure 26-19. RxFIFO (PSCRFDRn) and TxFIFO (PSCTFDRn) Data Register
26.3.3.23 Rx and Tx FIFO Status Register (PSCRFSRn, PSCTFSRn)
The FIFO status registers contain bits which provide information about the status of the FIFO controller.
Some of the bits of this register are used to generate DMA requests. This register applies to all modes.
15
14
13
R
IP
TXW
W w1c
w1c
Reset
0
0
0
Reg
MBAR + 0x8664 (PSCRFSR0); 0x8764 (PSCRFSR1); 0x8864 (PSCRFSR2); 0x8964 (PSCRFSR3)
Addr
and MBAR + 0x8684 (PSCTFSR0); 0x8784 (PSCTFSR1); 0x8884 (PSCTFSR2); 0x8984 (PSCTFSR3)
Figure 26-20. RxFIFO (PSCRFSR) and TxFIFO (PSCTFSR) Status Register
26-28
29
28
27
26
0
0
0
0
13
12
11
10
0
0
0
0
12
11
10
TAG
FRM
0
0
0
MCF548x Reference Manual, Rev. 3
25
24
23
22
DATA
0
0
0
0
9
8
7
6
DATA
0
0
0
0
9
8
7
6
FAE
RXW
w1c
w1c
0
0
0
0
(PSCTBn)", for more
21
20
19
18
0
0
0
0
5
4
3
2
0
0
0
0
5
4
3
2
UF
OF
FRM
FU
RDY
w1c
w1c
0
0
0
0
Freescale Semiconductor
17
16
0
0
1
0
0
0
1
0
ALARM EMT
0
1
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