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ESAI Programming Model
8.3.1.2
TCCR Transmit Prescaler Range (TPSR) - Bit 8
The TPSR bit controls a fixed divide-by-eight prescaler in series with the variable prescaler. This bit is used to extend the range of the prescaler
for those cases where a slower bit clock is desired. When TPSR is set, the fixed prescaler is bypassed. When TPSR is cleared, the fixed
divide-by-eight prescaler is operational (see
internally generated bit clock frequency is Fosc/(2 x 8 x 256)=Fosc/4096.
Do not use the combination TPSR=1, TPM7-TPM0=$00, and TFP3-TFP0=$0 which causes
synchronization problems when using the internal DSP clock as source (TCKD=1 or THCKD=1).
8.3.1.3
TCCR Tx Frame Rate Divider Control (TDC4–TDC0) - Bits 13–9
The TDC4–TDC0 bits control the divide ratio for the programmable frame rate dividers used to generate the transmitter frame clocks.
In network mode, this ratio may be interpreted as the number of words per frame minus one. The divide ratio may range from 2 to 32
(TDC[4:0]=00001 to 11111) for network mode. A divide ratio of one (TDC[4:0]=00000) in network mode is a special case (on-demand mode).
In normal mode, this ratio determines the word transfer rate. The divide ratio may range from 1 to 32 (TDC[4:0]=00000 to 11111) for normal
mode. In normal mode, a divide ratio of 1 (TDC[4:0]=00000) provides continuous periodic data word transfers. A bit-length frame sync
(TFSL=1) must be used in this case.
The ESAI frame sync generator functional diagram is shown in
RDC0 - RDC4
RX WORD
CLOCK
RECEIVER
FRAME RATE
DIVIDER
RECEIVE
CONTROL
LOGIC
TDC0 - TDC4
TX WORD
CLOCK
TRANSMITTER
FRAME RATE
DIVIDER
TRANSMIT
CONTROL
LOGIC
Figure 8-4. ESAI Frame Sync Generator Functional Block Diagram
8.3.1.4
TCCR Tx High Frequency Clock Divider (TFP3-TFP0) - Bits 17–14
The TFP3–TFP0 bits control the divide ratio of the transmitter high frequency clock to the transmitter serial bit clock when the source of the
high frequency clock and the bit clock is the internal DSP clock. When the HCKT input is being driven from an external high frequency clock,
the TFP3-TFP0 bits specify an additional division ratio in the clock divider chain. See
ESAI high frequency clock generator functional diagram is shown in
8-8
Figure
8-3). The maximum internally generated bit clock frequency is Fosc/4; the minimum
NOTE
Figure
8-4.
RFSL
INTERNAL RX FRAME CLOCK
SYNC
TYPE
RFSD=1
SYN=0
RECEIVE
FRAME SYNC
RFSD=0
SYN=1
TFSL
INTERNAL TX FRAME CLOCK
SYNC
TYPE
TRANSMIT
FRAME SYNC
Figure
DSP56374 Users Guide, Rev. 1.2
SYN=0
SYN=1
FLAG1 IN
FLAG1OUT
(SYNC MODE)
(SYNC MODE)
Table 8-3
for the specification of the divide ratio. The
8-3.
RFSD
FSR
TFSD
FST
Freescale Semiconductor
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