Dpu Vtb Start Address Register (Dp_Tsa) - Freescale Semiconductor MSC8144E Reference Manual

Debugging, Profiling, and Performance Monitoring
Name Reset
EN 0 Enable
0 This bit is used to enable/disable the trace buffer.
Use the following guidelines to enable/disable the
trace buffer:
• Always wait until any current flush operations are
completed before disabling a trace operation. Poll
the DP_SR[TWBA] bit to determine the flush
status.
• To prevent any interrupt servicing that may occur
between reading the DP_SR[TWBA] bit and
disabling the trace buffer, always disable the
interrupts before reading the DP_SR[TWBA] bit
and enable them only after disabling the trace
buffer.
• Never change the configuration of a trace
operation during execution. Always disable the
trace buffer first and then change the
configuration.

25.2.14.21 DPU VTB Start Address Register (DP_TSA)

DP_TSA
Bit 31 30 29
Type
Reset 0 0 0
Bit 15 14 13
Type
Reset 0 0 0
The DP_TSA is a 32-bit register that contains the start address of the VTB (physical address). The VTB
can be located only in Bank 3 (between addresses 0x00000000–0xFF000000).
the burst size:
For a burst size of
the DP_TC register).
For a burst size of 4 VBRs, the value of TER can be 32 × (2 × n – 1), where n is a positive integer.
Note: Bits 4–0 must be written as zeros and are read as zeros.
Table 25-35 defines the DP_TSA bit fields.
25-64
Table 25-33. DP_TC Bit Descriptions (Continued)
Description
DPU VTB Start Address Register
28 27 26 25
0 0 0 0
12 11 10 9
SA
0 0 0 0
1 VBR, TER must be aligned to the value: 32 × Burst Size (programmed in
MSC8144E Reference Manual, Rev. 3
0 Trace buffer disabled.
1 Trace buffer enabled
24 23 22 21
SA
R/W
0 0 0 0
8 7 6 5
R/W
0 0 0 0
Settings
Offset 0x80
20 19 18 17
0 0 0 0
4 3 2 1
—
0 0 0 0
Alignment depends on
Freescale Semiconductor
16
0
0
0