Siu Module Configuration Register (Siumcr) - Freescale Semiconductor MPC850 User Manual

Programming the SIU
10.4.2 SIU Module Configuration Register (SIUMCR)
The SIU module configuration register (SIUMCR) contains bits that configure the
following features in the SIU:
• External bus arbitration
• External master support
• Debug and test port configuration
• System interface pin configuration
• Parity support
Bits 0 1
Field EARB EARP
n
Reset
R/W
Addr
Bits 16 17 18
Field OPAR PNCS DPC MPRE MLRC
Reset
R/W
Addr
Figure 10-3. SIU Module Configuration Register (SIUMCR)
Table 10-3 describes SIUMCR fields.
Bits Name
0 EARB External arbitration. For more information, see Section 13.4.6, "Arbitration Phase." The default value
depends on the reset configuration; see Section 11.3.1.1, "Hard Reset Configuration Word."
0 Internal arbitration is performed.
1 External arbitration is assumed.
1–3 EARP External arbitration request priority. Defines the priority of the external master's arbitration request
relative to requests by internal modules. Valid when EARB is cleared. 000 = lowest priority and 111
= highest (however, the internal UPM-based refresh cycles always have a higher priority and will
preempt any external master if the internal arbiter is used). See Figure 13-21 and Table 19-1.
4–7 — Reserved, should be cleared.
8 DSHW Data show cycles. Selects the show cycle mode to be applied to data cycles. Data show cycles do
not include CPU interaction with the data cache; they only include CPU interactions with peripherals
on the internal U-bus (that is, CPM and SIU). (Instruction show cycles are programmed in ICTRL
see the Hardware Specifications for more information.) This bit is locked by the DLK bit.
0 Disable show cycles for all internal data cycles.
1 Show address and data of all internal data cycles.
9–10 DBGC Debug pin configuration. The default is set by the hard reset configuration word. See
Section 11.3.1.1, "Hard Reset Configuration Word" for the description of these bits.
2 3 4 5 6
—
000_0000_0
(IMMR & 0xFFFF0000) + 0x000
19 20 21 22
AEME SEME —
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x002
Table 10-3. SIUMCR Field Descriptions
MPC850 Family User's Manual
7 8 9 10
DSHW DBGC
n
R/W
23 24 25 26
GB5E B2DD B3DD
R/W
Description
11 12 13 14 15
DBPC — FRC DLK
n
000
27 28 29 30 31
—