Arbiter Configuration Register (Xarb_Cfg) - Freescale Semiconductor MCF5480 Reference Manual

MBAR
Offset
0x258 Arbiter Address Timeout
0x25C Arbiter Data Timeout
0x260
0x264 Arbiter Master Priority Enable
0x268 Arbiter Master Priority

10.3.3.1 Arbiter Configuration Register (XARB_CFG)

The arbiter configuration register is used to enable watchdog functions and arbiter protocol functions.
31 30 29
R PLDIS 0 0
W
Reset 1 0 0
15 14 13
R 0 0 0
W
Reset 0 0 0
Reg
Addr
Bit Name
31 PLDIS
30–11 —
10–8 SP
7 —
6–5 PM[1:0]
Freescale Semiconductor
Table 10-4. XL Bus Arbiter Memory Map (Continued)
Name
Arbiter Bus Timeout
28 27 26
0 0 0
0 0 0
12 11 10
0 0
0 0 0
Figure 10-5. Arbiter Configuration Register (XARB_CFG)
Table 10-5. XARB_CFG Bit Descriptions
Pipeline Disable. This bit is used to control the pipeline functionality
0 Enable pipeline
1 Disable pipeline
Reserved, should be cleared.
Select Parked Master. These bits set the master that is used in Park on Programmed Master mode.
000 Master 0
001 Master 1
...
111 Master 7).
Reserved, should be cleared.
Parking Mode. Parking modes are detailed in
00 No parking (default)
01 Reserved
10 Park on most recently used master
11 Park on programmed master as specified by the Select Parked Master bits 21:23 above.
MCF548x Reference Manual, Rev. 3
Byte0 Byte1
XARB_ADRTO
XARB_DATTO
XARB_BUSTO
XARB_PRIEN
XARB_PRI
25 24 23 22
0 0 0 0
0 0 0 0
9 8 7 6
SP 0 PM
0 0 0 0
MBAR + 0x0240
Description
Section 10.3.2.2.2, "Parking Modes."
Byte2 Byte3 Access
21 20 19 18
0 0 0 0
0 0 0 0
5 4 3 2
0 BA DT
0 0 0 1
XL Bus Arbiter
R/W
R/W
R/W
R/W
R/W
17 16
0 0
0 0
1 0
AT 0
1 0
10-9