Mtim Clock Configuration Register (Mtimx_Clk) - Freescale Semiconductor MC9S08PT60 Reference Manual

13.6.2 MTIM Clock Configuration Register (MTIMx_CLK)

MTIM_CLK contains the clock select bits (CLKS) and the prescaler select bits (PS).
Address: Base address + 1h offset
Bit 7
Read 0
Write
Reset
0
Field
7–6 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
5–4 Clock Source Select
CLKS
These two read/write bits select one of four different clock sources as the input to the MTIM prescaler.
Changing the clock source while the counter is active does not clear the counter. The count continues with
the new clock source. Reset clears CLKS to 000b.
00 Encoding 0. Bus clock (BUSCLK).
01 Encoding 1. Fixed-frequency clock (XCLK).
10 Encoding 2. External source (TCLK pin), falling edge.
11 Encoding 3. External source (TCLK pin), rising edge.
PS Clock Source Prescaler
These four read/write bits select one of nine outputs from the 8-bit prescaler. Changing the prescaler value
while the counter is active does not clear the counter. The count continues with the new prescaler value.
Reset clears PS to 0000b.
0000 Encoding 0. MTIM clock source.
0001 Encoding 1. MTIM clock source/2.
0010 Encoding 2. MTIM clock source/4.
0011 Encoding 3. MTIM clock source/8.
0100 Encoding 4. MTIM clock source/16.
0101 Encoding 5. MTIM clock source/32.
0110 Encoding 6. MTIM clock source/64.
0111 Encoding 7. MTIM clock source/128.
1000 Encoding 8. MTIM clock source/256.
Others Default to MTIM clock source/256.
Freescale Semiconductor, Inc.
6 5 4
CLKS
0 0 0
MTIMx_CLK field descriptions
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
Chapter 13 8-bit modulo timer (MTIM)
3 2
0 0
Description
1 0
PS
0 0
401