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NOTE:
8.6.4 PLL Reference Divider Select Register (PRDS)
NOTE:
Advance Information
106
MUL[11:0] — Multiplier select bits
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier N. (See
Programming the
PLLON bit in the PCTL is set. A value of $0000 in the multiplier select
registers configures the modulo feedback divider the same as a value
of $0001. Reset initializes the registers to $002 for a default multiply
value of 2.
The multiplier select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1).
The PLL reference divider select register contains the programming
information for the modulo reference divider.
Address:
$003F
Bit 7
6
Read:
0
0
Write:
Reset:
0
0
= Unimplemented
Figure 8-6. PLL Reference Divider Select Register (PRDS)
RDS[3:0] — Reference Divider Select Bits
These read/write bits control the modulo reference divider that selects
the reference division factor R. (See
Programming the
PLLON bit in the PCTL is set. A value of $00 in the reference divider
select register configures the reference divider the same as a value of
$01. (See
8.4.7 Special Programming
initializes the register to $01 for a default divide value of 1.
The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
8.4.3 PLL Circuits
PLL.) MUL[11:0] cannot be written when the
5
4
3
0
0
RDS3
0
0
0
8.4.3 PLL Circuits
PLL.) RDS[7:0] cannot be written when the
and
8.4.6
2
1
Bit 0
RDS2
RDS1
RDS0
0
0
and
8.4.6
Exceptions.) Reset
MC68HC(7)08KH12
Rev. 1.1
—
Freescale Semiconductor
1
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