Adc Sample Time Register 2 (Adc_Smpr2); Adc Injected Channel Data Offset Register X (Adc_Jofrx) (X=1; Adc Watchdog Higher Threshold Register (Adc_Htr) - ST STM32F412 Reference Manual

RM0402
13.12.5

ADC sample time register 2 (ADC_SMPR2)

Address offset: 0x10
Reset value: 0x0000 0000
31 30 29
Res. Res. SMP9[2:0]
rw
15 14 13
SMP5_0 SMP4[2:0]
rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:0 SMPx[2:0]: Channel x sampling time selection
Note: 000: 3 cycles
13.12.6

ADC injected channel data offset register x (ADC_JOFRx) (x=1..4)

Address offset: 0x14-0x20
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 JOFFSETx[11:0]: Data offset for injected channel x
13.12.7

ADC watchdog higher threshold register (ADC_HTR)

Address offset: 0x24
Reset value: 0x0000 0FFF
28 27 26 25
SMP8[2:0]
rw rw rw rw
12 11 10
SMP3[2:0]
rw rw rw rw
These bits are written by software to select the sampling time individually for each channel.
During sample cycles, the channel selection bits must remain unchanged.
001: 15 cycles
010: 28 cycles
011: 56 cycles
100: 84 cycles
101: 112 cycles
110: 144 cycles
111: 480 cycles
27 26 25
Res. Res. Res.
11 10 9
rw rw rw
These bits are written by software to define the offset to be subtracted from the raw
converted data when converting injected channels. The conversion result can be read from
in the ADC_JDRx registers.
24 23 22
SMP7[2:0]
rw rw rw
9 8 7 6
SMP2[2:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
JOFFSETx[11:0]
rw rw rw
RM0402 Rev 6
Analog-to-digital converter (ADC)
21 20 19 18
SMP6[2:0]
rw rw rw
5 4 3
SMP1[2:0]
rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
17 16
SMP5[2:1]
rw rw rw
2 1 0
SMP0[2:0]
rw rw rw
17 16
Res. Res.
1 0
rw rw
339/1163
347