Adc Injected Channel Data Offset Register X (Adc_Jofrx) (X=1; Adc Watchdog Higher Threshold Register (Adc_Htr) - ST STM32F207 Series Reference Manual

RM0033
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:0 SMPx[2:0]: Channel x sampling time selection
Note: 000: 3 cycles
10.13.6

ADC injected channel data offset register x (ADC_JOFRx) (x=1..4)

Address offset: 0x14-0x20
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Reserved
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 JOFFSETx[11:0]: Data offset for injected channel x
10.13.7

ADC watchdog higher threshold register (ADC_HTR)

Address offset: 0x24
Reset value: 0x0000 0FFF
31 30 29 28
15 14 13 12
Reserved
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 HT[11:0]: Analog watchdog higher threshold
These bits are written by software to select the sampling time individually for each channel.
During sample cycles, the channel selection bits must remain unchanged.
001: 15 cycles
010: 28 cycles
011: 56 cycles
100: 84 cycles
101: 112 cycles
110: 144 cycles
111: 480 cycles
27 26 25
11 10 9
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These bits are written by software to define the offset to be subtracted from the raw
converted data when converting injected channels. The conversion result can be read from
in the ADC_JDRx registers.
27 26 25
11 10 9
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These bits are written by software to define the higher threshold for the analog watchdog.
24 23 22
Reserved
8 7 6
JOFFSETx[11:0]
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24 23 22
Reserved
8 7 6
HT[11:0]
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RM0033 Rev 9
Analog-to-digital converter (ADC)
21 20 19 18
5 4 3 2
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21 20 19 18
5 4 3 2
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17 16
1 0
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17 16
1 0
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