Rcc Apb1 Peripheral Reset Register For (Rcc_Apb1Rstr) - ST STM32F410 Reference Manual

Reset and clock control (RCC)
Bit 7 GPIOHRST: IO port H reset
0: does not reset IO port H
1: resets IO port H
Bits 6:3 Reserved, must be kept at reset value.
Bit 2 GPIOCRST: IO port C reset
Bit 1 GPIOBRST: IO port B reset
Bit 0 GPIOARST: IO port A reset
5.3.6

RCC APB1 peripheral reset register for (RCC_APB1RSTR)

Address offset: 0x20
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
DAC PWR
Res. Res.
RST RST
rw
15 14 13
SPI2
Res. Res. Res.
RST
rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DACRST: DAC reset
Set and cleared by software.
0: does not reset the DAC interface
1: resets the DAC interface
Bit 28 PWRRST: Power interface reset
Set and cleared by software.
0: does not reset the power interface
1: resets the power interface
Bits 27:25 Reserved, must be kept at reset value.
112/771
Set and cleared by software.
Set and cleared by software.
0: does not reset IO port C
1: resets IO port C
Set and cleared by software.
0: does not reset IO port B
1:resets IO port B
Set and cleared by software.
0: does not reset IO port A
1: resets IO port A
28 27 26 25
Res. Res. Res.
rw
12 11 10 9
WWDG LPTIM1
Res.
RST RST
rw rw
24 23 22
I2C4 I2C2
Res.
RST RST
rw rw
8 7 6
Res. Res. Res.
RM0401 Rev 3
21 20 19 18
I2C1
Res. Res. Res.
RST
rw
5 4 3 2
TIM6 TIM5
Res. Res.
RST RST
rw rw
RM0401
17 16
USART2
Res.
RST
rw
1 Res.
Res. Res.