Rcc Apb1 Peripheral Reset Register (Rcc_Apb1Rstr) - ST STM32F446 Series Reference Manual

RM0390
Bit 0 FMCRST: Flexible memory controller module reset
6.3.8

RCC APB1 peripheral reset register (RCC_APB1RSTR)

Address offset: 0x20
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28
DAC PWR
Res. Res.
RST RST
rw rw
15 14 13 12
SPI3 SPI2
Res. Res.
RST RST
rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DACRST: DAC reset
Set and cleared by software.
0: does not reset the DAC interface
1: resets the DAC interface
Bit 28 PWRRST: Power interface reset
Set and cleared by software.
0: does not reset the power interface
1: resets the power interface
Bit 27 CECRST: CEC reset
Set and cleared by software.
0: does not reset CEC
1: resets CEC
Bit 26 CAN2RST: CAN2 reset
Set and cleared by software.
0: does not reset CAN2
1: resets CAN2
Bit 25 CAN1RST: CAN1 reset
Set and cleared by software.
0: does not reset CAN1
1: resets CAN1
Bit 24 IFMPI2C1RST: FMPI2C1 reset
Set and cleared by software
0: does not reset FMPI2C1
1: resets FMPI2C1
Set and cleared by software.
0: does not reset the FMC module
1: resets the FMC module
27 26 25
CECRS CAN2 CAN1
T RST RST
rw rw
11 10 9
WWDG
Res. Res.
RST
rw
24 23 22
FMPI2C1 I2C3 I2C2 I2C1
RST RST RST
rw rw rw
8 7 6
TIM14 TIM13 TIM12 TIM7
RST RST RST
rw rw rw
RM0390 Rev 4
Reset and clock control (RCC)
21 20 19 18
UART5 UART4 UART3
RST RST RST RST
rw rw rw rw
5 4 3 2
TIM6 TIM5 TIM4
RST RST RST RST
rw rw rw rw
17 16
UART2 SPDIFRX
RST RST
rw rw
1 0
TIM3 TIM2
RST RST
rw rw
139/1328
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