Operation; Figure 9.20 Example Of Software Processing When Using Ech And Ecl As 16-Bit Event Counter - Renesas H8/3847R Series Hardware Manual

8-bit single-chip microcomputer super low power

Table of Contents

Bit 3: Asynchronous event counter module standby mode control (AECKSTP)

Bit 3 controls setting and clearing of module standby mode for the asynchronous event counter.

Asynchronous event counter is set to module standby mode

Asynchronous event counter module standby mode is cleared

Operation

1. 16-bit Event Counter Operation

When bit CH2 is cleared to 0 in ECCSR, ECH and ECL, operate as a 16-bit event counter. Figure

9.20 shows an example of the software processing when ECH and ECL are used as a 16-bit event

Figure 9.20 Example of Software Processing when Using ECH and ECL as 16-Bit Event

As CH2 is cleared to 0 by a reset, ECH and ECL operate as a 16-bit event counter after a reset.

They can also be used as a 16-bit event counter by carrying out the software processing shown in

the example in figure 9.20. The operating clock source is asynchronous event input from the

AEVL pin. When the next clock is input after the count value reaches H'FF in both ECH and

ECL, ECH and ECL overflow from H'FFFF to H'0000, the OVH flag is set to 1 in ECCSR, the

ECH and ECL count values each return to H'00, and counting up is restarted. When overflow

Clear CH2 to 0

Clear CUEH, CUEL, CRCH, and CRCL to 0

Clear OVH and OVL to 0

Set CUEH, CUEL, CRCH, and CRCL to 1

Rev. 6.00 Aug 04, 2006 page 327 of 680

Section 9 Timers

(initial value)

REJ09B0145-0600