Noise Canceler - Hitachi H8/3937 Series Hardware Manual

5. Clock stop register 1 (CKSTPR1)
Bit 7
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value 1
Read/Write R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer G is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 3: Timer G module standby mode control (TGCKSTP)
Bit 3 controls setting and clearing of module standby mode for timer G.
TGCKSTP Description
0 Timer G is set to module standby mode
1 Timer G module standby mode is cleared
9.5.3

Noise Canceler

The noise canceler consists of a digital low-pass filter that eliminates high-frequency component
noise from the pulses input from the input capture input pin. The noise canceler is set by NCS* in
PMR3.
Figure 9-9 shows a block diagram of the noise canceler.
Sampling
clock
C
Input capture
D Q
input signal
Latch
Sampling clock
∆t: Set by CKS1 and CKS0
6 5
1 1
R/W R/W
C C
D Q D Q
Latch Latch
∆t
Figure 9-9 Noise Canceler Block Diagram
4 3
1 1
R/W R/W R/W
C C
D Q D Q
Latch Latch
2 1 0
1 1 1
R/W R/W
(initial value)
Noise
Match
canceler
detector
output
221