Mmu Data Cam Entry Read Register - Freescale Semiconductor PowerPC MPC823 Reference Manual

Memory Management Unit
11.6.2.1 MMU DATA CAM ENTRY READ REGISTER. When the content-addressable
memory of the MMU data CAM entry read (MD_CAM) register is read, it contains the
effective address and page sizes of an entry indexed by the DTLB_INDX field of the
MD_CTR. This register is only updated when you write a value to it.
MD_CAM
BIT 0 1 2
FIELD
RESET
R/W
ADDR
BIT 16 17 18
FIELD EPN
RESET —
R/W R
ADDR
NOTE: — = Undefined.
EPN—Effective Page Number
These bits are the most-significant bits of the page's effective address.
SPVF—Subpage Validity Flags
For Bit 20:
0 = Subpage 0 (address[20:21] = 00) is not valid.
1 = Subpage 0 (address[20:21] = 00) is valid.
For Bit 21:
0 = Subpage 1 (address[20:21] = 01) is not valid.
1 = Subpage 1 (address[20:21] = 01) is valid.
For Bit 22:
0 = Subpage 2 (address[20:21] = 10) is not valid.
1 = Subpage 2 (address[20:21] = 10) is valid.
For Bit 23:
0 = Subpage 3 (address[20:21] = 11) is not valid.
1 = Subpage 3 (address[20:21] = 11) is valid.
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3 4 5 6
19 20 21 22
SPVF
—
R
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7 8 9 10 11
EPN
—
R
SPR 824
23 24 25 26 27
PS SH
— —
R R
SPR 824
12 13 14 15
28 29 30 31
ASID
—
R
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