Data Synchronization Register (Dsr) - Freescale Semiconductor MPC850 User Manual

Table 21-2. GSMR_L Field Descriptions (Continued)
Bit Name
27 ENT Enable transmit. Enables the transmitter hardware state machine for the SCC.
0 The transmitter is disabled. If ENT is cleared during transmission, the current character is aborted
and TXD returns to the idle state. Data already in the Tx shift register is not sent.
1 The transmitter is enabled.
ENT can be set or cleared, regardless of whether serial clocks are present. Section 21.4.7,
"Reconfiguring the SCCs," describes how to disable/enable the SCCs. Note also these other tools
provided for controlling SCC transmission: the
RESTART TRANSMIT
TxBD[R].
28–31 MODE Channel protocol mode. See also GSMR_H[TTX, TRX].
0000 HDLC
0001 Reserved
0010 AppleTalk/LocalTalk
0011 SS7—reserved for RAM microcode
0100 UART
0101 Reserved
0110 Asynchronous HDLC or IrDA
0111 V.14—reserved for RAM microcode
1000 BISYNC
1001 DDCMP—reserved for RAM microcode
101x Reserved
1100 Ethernet
All others reserved.
21.2.2 Protocol-Specific Mode Register (PSMR)
The protocol implemented by an SCC is selected by its GSMR_L[MODE]. Each SCC has
an additional protocol-specific mode register (PSMR) for configurations specific to the
chosen protocol. The PSMR fields are described in the specific chapters that describe each
protocol.

21.2.3 Data Synchronization Register (DSR)

Each SCC has a data synchronization register (DSR) that specifies the pattern used for
frame synchronization. The programmed value for DSR depends on the protocol:
• UART—DSR is used to configure fractional stop bit transmission.
• BISYNC and transparent—DSR should be programmed with the sync pattern.
• Ethernet—DSR should be programmed with 0xD555.
• HDLC—At reset, DSR defaults to 0x7E7E (two HDLC flags), so it does not need to
be written.
commands, the freeze option and CTS flow control option in UART mode, and
Chapter 21. Serial Communications Controllers
Description
,
STOP TRANSMIT GRACEFUL STOP TRANSMIT
SCC Registers
, and