Extended Next Link Descriptor Address Registers (Enlndarn) - Freescale Semiconductor MSC8144E Reference Manual

RapidIO Interface Dedicated DMA Controller

17.3.12 Extended Next Link Descriptor Address Registers (ENLNDARn)

ENLNDAR0 Extended Next Link Descriptor Address Registers 0–3
ENLNDAR1
ENLNDAR2
ENLNDAR3
Bit 31 30 29
Type
Reset 0 0 0
Bit 15 14 13
Type
Reset 0 0 0
The ENLNDAR contains the extended address of the next link descriptor for the specified
channel.
Note: These registers are only used for RapidIO transactions. They are not used for accesses
to the internal RapidIO address space.
For RapidIO transactions in basic chaining mode, software must initialize this register and the
NLNDAR to point to the next link descriptor in memory. After the current descriptor is
processed, the ECLNDAR and CLNDAR are loaded from the ENLNDAR and the NLNDAR.
Then the controller evaluates the NLNDARn[EOLND] field. If EOLND is cleared (0), the DMA
controller reads in the new current link descriptor for processing. If EOLND is set (1), the last
descriptor of the list has completed. If extended chaining mode is not enabled, all DMA transfers
are complete and the DMA controller halts.
If extended chaining mode is enabled, the DMA controller examines the state of the EOLSD bit
in the next list descriptor address register (NLSDAR). If EOLSD is clear, the controller loads the
contents of the ENLSDAR into the ECLSDAR and the contents of the NLSDAR into the
CLSDAR and reads the new list descriptor from memory. If EOLSD is set, all DMA transfers are
complete and the DMA controller halts. Table 17-16 describes the ENLNDAR fields.
Bits Reset
—
0
31–4
ENLNDA 0
3–0
17-34
28 27 26 25
0 0 0 0
12 11 10 9
—
0 0 0 0
Table 17-16. ENLNDAR Field Descriptions
Description
Reserved. Write to zero for future compatibility.
Next Link Descriptor Extended Address
Contains the most significant 4 bits of the 36-bit
address used with RapidIO transactions only.
Note: This field is not used for local
transactions.
MSC8144E Reference Manual, Rev. 3
24 23 22 21
—
R/W
0 0 0 0
8 7 6 5
R/W
0 0 0 0
Offset 0x124
Offset 0x1A4
Offset 0x224
Offset 0x2A4
20 19 18 17
0 0 0 0
4 3 2 1
ENLNDA
0 0 0 0
Setting
Freescale Semiconductor
16
0
0
0