Port D Direction Register (Prrd); Figure 10-7 Port D Direction Register (Prrd); Table 10-6 Dax Port Gpio Control Register Functionality - Freescale Semiconductor DSP56366 User Manual

PCRD -Port D Control Register - X:$FFFFD7
23 22 21 20 19 18
read as zero, should be written with zero for future compatibility
10.7.2

Port D Direction Register (PRRD)

The read/write 24-bit Port D Direction Register controls the direction of the DAX GPIO pins. When port
pin[i] is configured as GPIO, PDC[i] controls the port pin direction. When PDC[i] is set, the GPIO port
pin[i] is configured as output. When PDC[i] is cleared the GPIO port pin[i] is configured as input.
Hardware and software reset clear all PRRD bits.
PRRD - Port D Direction Register - X:$FFFFD6
23 22 21 20 19 18
read as zero, should be written with zero for future compatibility
PDC1 PC1
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
Freescale Semiconductor
17 16 15 14
17 16 15 14 13

Figure 10-7 Port D Direction Register (PRRD)

Table 10-6 DAX Port GPIO Control Register Functionality

ADO/PD1 pin PDC0
Disconnected
Disconnected
Disconnected
Disconnected
PD1 Input
PD1 Input
PD1 Input
PD1 Input
PD1 Output
PD1 Output
PD1 Output
PD1 Output
ADO
ADO
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
13 12 11 10 9 8 7
Table 10-6 describes the port pin configurations.
12 11 10 9 8 7
PC0 ACI/PD0 pin
0 0 Disconnected
0 1 PD0 Input
1 0 PD0 Output
1 1 ACI
0 0 Disconnected
0 1 PD0 Input
1 0 PD0 Output
1 1 ACI
0 0 Disconnected
0 1 PD0 Input
1 0 PD0 Output
1 1 ACI
0 0 Disconnected
0 1 PD0 Input
GPIO (PORT D) - Pins and Registers
6 5 4 3 2 1 0
PC1 PC0
6 5 4 3 2 1 0
PDC1 PDC0
DAX state
Personal Reset
Personal Reset
Personal Reset
Enabled
Personal Reset
Personal Reset
Personal Reset
Enabled
Personal Reset
Personal Reset
Personal Reset
Enabled
Enabled
Enabled
10-13