Table of Contents
Advertisement
5.3.6 Reset Control Enable Register (RCER)
RCER
Bit
31
30
29
Type
Reset
0
0
0
Bit
15
14
13
Type
Reset
0
0
0
The reset control enable register shown in indicates by the CRE field that the reset protection
register (RPR) was accessed with a value that enables the reset control register (RCR). Table
5-14 defines the RCER bit fields.
Name
Reset
—
0
Reserved. Write to zero for future compatibility.
31–1
CRE
0
Control Register Enabled
0
Indicates the status of the reset control register
(RCR). Writing 1 to this bit disables the RCR
and clears this bit. Writing zero has no effect.
Freescale Semiconductor
Reset Control Enable Register
28
27
26
25
0
0
0
0
12
11
10
9
0
0
0
0
Table 5-14. RCER Bit Descriptions
Description
MSC8144E Reference Manual, Rev. 3
24
23
22
21
—
R/W
0
0
0
0
8
7
6
5
—
R/W
0
0
0
0
0
RCR is disabled.
1
The enable value is written to the reset
protection register (RPR) to enable the RCR.
Reset Programming Model
Offset 0x20
20
19
18
17
0
0
0
0
4
3
2
1
CRE
0
0
0
0
Settings
16
0
0
0
5-25
Advertisement
Table of Contents
