STMicroelectronics STM32WL5 Series Reference Manual page 1186

Universal synchronous/asynchronous receiver transmitter (USART/UART)
Bit 22 REACK: Receive enable acknowledge flag
Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and
Bit 21 TEACK: Transmit enable acknowledge flag
Bit 20 WUF: Wake-up from low-power mode flag
Note: When UESM is cleared, WUF flag is also cleared.
Bit 19 RWU: Receiver wake-up from Mute mode
Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and
Bit 18 SBKF: Send break flag
Bit 17 CMF: Character match flag
Bit 16 BUSY: Busy flag
1186/1450
This bit is set/reset by hardware, when the Receive Enable value is taken into account by
the USART.
It can be used to verify that the USART is ready for reception before entering low-power
mode.
kept at reset value. Refer to
This bit is set/reset by hardware, when the Transmit Enable value is taken into account by
the USART.
It can be used when an idle frame request is generated by writing TE = 0, followed by
TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period.
This bit is set by hardware, when a wake-up event is detected. The event is defined by the
WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register.
An interrupt is generated if WUFIE = 1 in the USART_CR3 register.
If the USART does not support the wake-up from Stop feature, this bit is reserved and
kept at reset value. Refer to
This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wake-
up/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is
selected by the WAKE bit in the USART_CR1 register.
When wake-up on IDLE mode is selected, this bit can only be set by software, writing 1 to
the MMRQ bit in the USART_RQR register.
0: Receiver in active mode
1: Receiver in Mute mode
kept at reset value. Refer to
This bit indicates that a send break character was requested. It is set by software, by writing
1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during
the stop bit of break transmission.
0: Break character transmitted
1: Break character requested by setting SBKRQ bit in USART_RQR register
This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is
cleared by software, writing 1 to the CMCF in the USART_ICR register.
An interrupt is generated if CMIE = 1in the USART_CR1 register.
0: No Character match detected
1: Character Match detected
This bit is set and reset by hardware. It is active when a communication is ongoing on the
RX line (successful start bit detected). It is reset at the end of the reception (successful or
not).
0: USART is idle (no reception)
1: Reception on going
Section 35.4: USART implementation on page
Section 35.4: USART implementation on page
Section 35.4: USART implementation on page
RM0453 Rev 5
RM0453
1116.
1116.
1116.