STMicroelectronics STM32WL5 Series Reference Manual page 1196

Universal synchronous/asynchronous receiver transmitter (USART/UART)
Bits 16:14 Reserved, must be kept at reset value.
Bit 13 UDRCF:SPI slave underrun clear flag
Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at
Bit 12 EOBCF: End of block clear flag
Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept
Bit 11 RTOCF: Receiver timeout clear flag
Note: If the USART does not support the Receiver timeout feature, this bit is reserved and
Bit 10 Reserved, must be kept at reset value.
Bit 9 CTSCF: CTS clear flag
Note: If the hardware flow control feature is not supported, this bit is reserved and must be
Bit 8 LBDCF: LIN break detection clear flag
Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer
Bit 7 TCBGTCF: Transmission complete before Guard time clear flag
Bit 6 TCCF: Transmission complete clear flag
Bit 5 TXFECF: TXFIFO empty clear flag
Bit 4 IDLECF: Idle line detected clear flag
Bit 3 ORECF: Overrun error clear flag
Bit 2 NECF: Noise detected clear flag
Bit 1 FECF: Framing error clear flag
Bit 0 PECF: Parity error clear flag
1196/1450
Writing 1 to this bit clears the UDRF flag in the USART_ISR register.
reset value. Refer to
Writing 1 to this bit clears the EOBF flag in the USART_ISR register.
at reset value. Refer to
Writing 1 to this bit clears the RTOF flag in the USART_ISR register.
must be kept at reset value. Refer to
page 1116.
Writing 1 to this bit clears the CTSIF flag in the USART_ISR register.
kept at reset value. Refer to
Writing 1 to this bit clears the LBDF flag in the USART_ISR register.
to Section 35.4: USART implementation on page
Writing 1 to this bit clears the TCBGT flag in the USART_ISR register.
Writing 1 to this bit clears the TC flag in the USART_ISR register.
Writing 1 to this bit clears the TXFE flag in the USART_ISR register.
Writing 1 to this bit clears the IDLE flag in the USART_ISR register.
Writing 1 to this bit clears the ORE flag in the USART_ISR register.
Writing 1 to this bit clears the NE flag in the USART_ISR register.
Writing 1 to this bit clears the FE flag in the USART_ISR register.
Writing 1 to this bit clears the PE flag in the USART_ISR register.
Section 35.4: USART implementation on page 1116
Section 35.4: USART implementation on page
Section 35.4: USART implementation on
Section 35.4: USART implementation on page
RM0453 Rev 5
1116.
1116.
RM0453
1116.