STMicroelectronics STM32WL5 Series Reference Manual page 1165

RM0453
2. RXFF flag is asserted if the USART receives n+1 data (n being the RXFIFO size): n data in the RXFIFO and 1 data in
USART_RDR. In Stop mode, USART_RDR is not clocked. As a result, this register is not written and once n data are
received and written in the RXFIFO, the RXFF interrupt is asserted (RXFF flag is not set).
3. When OVRDIS = 0.
35.8 USART registers
Refer to
The peripheral registers have to be accessed by words (32 bits).
35.8.1 USART control register 1 (USART_CR1)
Address offset: 0x00
Reset value: 0x0000 0000
The same register can be used in FIFO mode enabled (this section) and FIFO mode
disabled (next section).
FIFO mode enabled
31 30 29
RXF FIFO
TXFEIE
FIE EN
rw rw rw
15 14 13
OVER8 CMIE MME
rw rw rw
Bit 31 RXFFIE: RXFIFO full interrupt enable
Bit 30 TXFEIE: TXFIFO empty interrupt enable
Bit 29 FIFOEN: FIFO mode enable
Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode
Universal synchronous/asynchronous receiver transmitter (USART/UART)
Section 1.2 on page 59
28 27 26 25
M1 EOBIE RTOIE
rw rw rw rw
12 11 10 9
M0 WAKE PCE PS
rw rw rw rw
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated when RXFF = 1 in the USART_ISR register
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated when TXFE = 1 in the USART_ISR register
This bit is set and cleared by software.
0: FIFO mode is disabled.
1: FIFO mode is enabled.
This bitfield can only be written when the USART is disabled (UE = 0).
and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.
for a list of abbreviations used in register descriptions.
24 23 22
DEAT[4:0]
rw rw rw
8 7 6
TXFNFI RXFNE
PEIE TCIE
E
rw rw rw
RM0453 Rev 5
21 20 19 18
DEDT[4:0]
rw rw rw rw
5 4 3 2
IDLEIE TE RE
IE
rw rw rw rw
17 16
rw rw
1 0
UESM UE
rw rw
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